1 /*
2 * Copyright (c) 2010 by Texas Instruments and others.
3 * All rights reserved. This program and the accompanying materials
4 * are made available under the terms of the Eclipse Public License v1.0
5 * which accompanies this distribution, and is available at
6 * http://www.eclipse.org/legal/epl-v10.html
7 *
8 * Contributors:
9 * Texas Instruments - initial implementation
10 *
11 * */
12
13 /*
14 * ======== ITMS320CTCI6486.xdc ========
15 *
16 */
17
18 /*!
19 * ======== ITMS320CTCI6486 ========
20 * An interface implemented by TCI6486 like devices
21 *
22 */
23 metaonly interface ITMS320CTCI6486 inherits ti.catalog.ICpuDataSheet
24 {
25 config long cacheSizeL1[string] = [
26 ["0k", 0x0000],
27 ["4k", 0x1000],
28 ["8k", 0x2000],
29 ["16k", 0x4000],
30 ["32k", 0x8000],
31 ];
32
33 config long cacheSizeL2[string] = [
34 ["0k", 0x00000],
35 ["32k", 0x08000],
36 ["64k", 0x10000],
37 ["128k", 0x20000],
38 ["256k", 0x40000]
39 ];
40
41 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] =
42
43 [
44 ['l1PMode',{desc:"L1P Cache",
45 base:0xE00000,
46 map : [["0k",0x0000],
47 ["4k",0x1000],
48 ["8k",0x2000],
49 ["16k",0x4000],
50 ["32k",0x8000]],
51 defaultValue: "32k",
52 memorySection: "L1PSRAM"}],
53
54 ['l1DMode',{desc:"L1D Cache",
55 base:0xF00000,
56 map : [["0k",0x0000],
57 ["4k",0x1000],
58 ["8k",0x2000],
59 ["16k",0x4000],
60 ["32k",0x8000]],
61 defaultValue: "32k",
62 memorySection: "L1DSRAM"}],
63
64 ['l2Mode',{desc:"L2 Cache",
65 base:0x00800000,
66 map : [["0k",0x0000],
67 ["32k",0x8000],
68 ["64k",0x10000],
69 ["128k",0x20000],
70 ["256k",0x40000]],
71 defaultValue: "0k",
72 memorySection: "LL2RAM"}],
73
74 ];
75
76 instance:
77
78 override config string cpuCore = "64x+";
79 override config string isa="64P";
80 override config string cpuCoreRevision = "1.0";
81
82 override config int minProgUnitSize = 1;
83 override config int minDataUnitSize = 1;
84 override config int dataWordSize = 4;
85
86 /*!
87 * ======== memMap ========
88 * The default memory map for this device
89 */
90 config xdc.platform.IPlatform.Memory memMap[string] = [
91 ["LL2RAM", {
92 comment: "608K Local L2 RAM/CACHE memory",
93 name: "LL2RAM",
94 base: 0x00800000,
95 len: 0x00098000,
96 space: "code/data",
97 access: "RWX"
98 }],
99
100 ["L1PSRAM", {
101 comment: "Internal 32KB RAM/CACHE L1 program memory",
102 name: "L1PSRAM",
103 base: 0xE00000,
104 len: 0x008000,
105 space: "code",
106 access: "RWX"
107 }],
108
109 ["L1DSRAM", {
110 comment: "Internal 32KB RAM/CACHE L1 data memory",
111 name: "L1DSRAM",
112 base: 0xF00000,
113 len: 0x008000,
114 space: "data",
115 access: "RW"
116 }],
117
118 ["SL2RAM", {
119 comment: "768K Shared L2 RAM memory",
120 name: "SL2RAM",
121 base: 0x00200000,
122 len: 0x000C0000,
123 space: "code/data",
124 access: "RWX"
125 }],
126 ];
127 };
128 /*
129 * @(#) ti.catalog.c6000; 1, 0, 0, 0,295; 12-3-2010 11:44:01; /db/ztree/library/trees/platform/platform-l29x/src/
130 */
131