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13 14 15 16
17 package ti.catalog.c6000;
18
19 /*!
20 * ======== ITMS320CTCI6484 ========
21 */
22 metaonly interface ITMS320CTCI6484 inherits ti.catalog.ICpuDataSheet
23 {
24
25 config long cacheSizeL1[string] = [
26 ["0k", 0x0000],
27 ["4k", 0x1000],
28 ["8k", 0x2000],
29 ["16k", 0x4000],
30 ["32k", 0x8000],
31 ];
32
33 config long cacheSizeL2[string] = [
34 ["0k", 0x000000],
35 ["32k", 0x008000],
36 ["64k", 0x010000],
37 ["128k", 0x020000],
38 ["256k", 0x040000],
39 ["512k", 0x080000],
40 ["1024k", 0x100000]
41 ];
42
43 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
44 ['l1PMode',{desc:"L1P Cache",
45 base: 0xE00000,
46 map : [["0k",0x0000],
47 ["4k",0x1000],
48 ["8k",0x2000],
49 ["16k",0x4000],
50 ["32k",0x8000]],
51 defaultValue: "32k",
52 memorySection: "L1PSRAM"}],
53
54 ['l1DMode',{desc:"L1D Cache",
55 base:0xF00000,
56 map : [["0k",0x0000],
57 ["4k",0x1000],
58 ["8k",0x2000],
59 ["16k",0x4000],
60 ["32k",0x8000]],
61 defaultValue: "32k",
62 memorySection: "L1DSRAM"}],
63
64 ['l2Mode',{desc:"L2 Cache",
65 base:0x800000,
66 map : [["0k",0x0000],
67 ["32k",0x8000],
68 ["64k",0x10000],
69 ["128k",0x20000],
70 ["256k",0x40000],
71 ["512k", 0x080000],
72 ["1024k", 0x100000]],
73 defaultValue: "0k",
74 memorySection: "IRAM"}],
75
76 ];
77
78 instance:
79
80 override config string cpuCore = "64x+";
81 override config string isa = "64P";
82 override config string cpuCoreRevision = "1.0";
83
84 override config int minProgUnitSize = 1;
85 override config int minDataUnitSize = 1;
86 override config int dataWordSize = 4;
87
88 /*!
89 * ======== memMap ========
90 * The default memory map for this device
91 */
92 config xdc.platform.IPlatform.Memory memMap[string] = [
93 ["IRAM", {
94 comment: "Internal 2MB L2 memory",
95 name: "IRAM",
96 base: 0x800000,
97 len: 0x200000,
98 space: "code/data",
99 access: "RWX"
100 }],
101
102 ["L1PSRAM", {
103 comment: "Internal 32KB RAM/CACHE L1 program memory",
104 name: "L1PSRAM",
105 base: 0xE00000,
106 len: 0x008000,
107 space: "code",
108 access: "RWX"
109 }],
110
111 ["L1DSRAM", {
112 comment: "Internal 32KB RAM/CACHE L1 data memory",
113 name: "L1DSRAM",
114 base: 0xF00000,
115 len: 0x008000,
116 space: "data",
117 access: "RW"
118 }],
119
120 ];
121 };
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