1 /*
2 * Copyright (c) 2010 by Texas Instruments and others.
3 * All rights reserved. This program and the accompanying materials
4 * are made available under the terms of the Eclipse Public License v1.0
5 * which accompanies this distribution, and is available at
6 * http://www.eclipse.org/legal/epl-v10.html
7 *
8 * Contributors:
9 * Texas Instruments - initial implementation
10 *
11 * */
12
13 /*
14 * ======== ITMS320CDRx40x.xdc ========
15 *
16 */
17
18 /*!
19 * ======== ITMS320CDRx40x ========
20 * An interface implemented by all DRx40x and DRx41x devices
21 *
22 * This interface is defined to factor common data about all DRA40x and
23 * DRA41x devices into a single file; they are all configured in the same way.
24 */
25 metaonly interface ITMS320CDRx40x inherits ti.catalog.ICpuDataSheet
26 {
27 config long cacheSizeL1[string] = [
28 ["0k", 0x0000],
29 ["4k", 0x1000],
30 ["8k", 0x2000],
31 ["16k", 0x4000],
32 ["32k", 0x8000],
33 ];
34
35 config long cacheSizeL2[string] = [
36 ["0k", 0x00000],
37 ["32k", 0x08000],
38 ["64k", 0x10000],
39 ["128k",0x20000],
40 ];
41
42 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
43 ['l1PMode',{desc:"L1P Cache",
44 base:0x11E00000,
45 map : [["0k",0x0000],
46 ["4k",0x1000],
47 ["8k",0x2000],
48 ["16k",0x4000],
49 ["32k",0x8000]],
50 defaultValue: "32k",
51 memorySection: "L1PSRAM"}],
52
53 ['l1DMode',{desc:"L1D Cache",
54 base:0x11F00000,
55 map : [["0k",0x0000],
56 ["4k",0x1000],
57 ["8k",0x2000],
58 ["16k",0x4000],
59 ["32k",0x8000]],
60 defaultValue: "32k",
61 memorySection: "L1DSRAM"}],
62
63 ['l2Mode',{desc:"L2 Cache",
64 base: 0x11810000,
65 map : [["0k",0x0000],
66 ["32k",0x8000],
67 ["64k",0x10000],
68 ["128k",0x20000]],
69 defaultValue: "0k",
70 memorySection: "IRAM"}]
71
72 ];
73
74 instance:
75
76 override config string cpuCore = "64x+";
77 override config string isa = "64P";
78 override config string cpuCoreRevision = "1.0";
79
80 override config int minProgUnitSize = 1;
81 override config int minDataUnitSize = 1;
82 override config int dataWordSize = 4;
83
84 /*!
85 * ======== memMap ========
86 * The default memory map for this device
87 */
88 config xdc.platform.IPlatform.Memory memMap[string] = [
89 ["IRAM", {
90 comment: "Internal 192KB UMAP0 memory",
91 name: "IRAM",
92 base: 0x11810000,
93 len: 0x00030000,
94 space: "code/data",
95 access: "RWX"
96 }],
97
98 ["L1PSRAM", {
99 comment: "Internal 16KB RAM/CACHE L1 program memory",
100 name: "L1PSRAM",
101 base: 0x11E00000,
102 len: 0x00004000,
103 space: "code",
104 access: "RWX"
105 }],
106
107 ["L1DSRAM", {
108 comment: "Internal 32KB RAM/CACHE L1 data memory",
109 name: "L1DSRAM",
110 base: 0x11F00000,
111 len: 0x00008000,
112 space: "data",
113 access: "RW"
114 }],
115
116 ["ARM_RAM", {
117 comment: "Internal ARM RAM memory",
118 name: "ARM_RAM",
119 base: 0x10008000,
120 len: 0x00004000,
121 space: "data",
122 access: "RW"
123 }],
124 ];
125 };
126 /*
127 * @(#) ti.catalog.c6000; 1, 0, 0, 0,295; 12-3-2010 11:44:01; /db/ztree/library/trees/platform/platform-l29x/src/
128 */
129