1 /*
2 * Copyright (c) 2010 by Texas Instruments and others.
3 * All rights reserved. This program and the accompanying materials
4 * are made available under the terms of the Eclipse Public License v1.0
5 * which accompanies this distribution, and is available at
6 * http://www.eclipse.org/legal/epl-v10.html
7 *
8 * Contributors:
9 * Texas Instruments - initial implementation
10 *
11 * */
12
13 /*
14 * ======== ITMS320CDRA45x.xdc ========
15 *
16 */
17
18 /*!
19 * ======== ITMS320CDRA45x ========
20 * An interface implemented by all DRA45x devices
21 *
22 * This interface is defined to factor common data about all DRA45x devices
23 * into a single place; they are all the same from the configuration point of
24 * view.
25 */
26 metaonly interface ITMS320CDRA45x inherits ti.catalog.ICpuDataSheet
27 {
28 config long cacheSizeL1[string] = [
29 ["0k", 0x0000],
30 ["4k", 0x1000],
31 ["8k", 0x2000],
32 ["16k", 0x4000],
33 ["32k", 0x8000],
34 ];
35
36 config long cacheSizeL2[string] = [
37 ["0k", 0x00000],
38 ["32k", 0x08000],
39 ["64k", 0x10000],
40 ["128k", 0x20000]
41 ];
42
43 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
44 ['l1PMode',{desc:"L1P Cache",
45 base:0x11E08000,
46 map : [["0k",0x0000],
47 ["4k",0x1000],
48 ["8k",0x2000],
49 ["16k",0x4000],
50 ["32k",0x8000]],
51 defaultValue: "32k",
52 memorySection: "L1PSRAM"}],
53
54 ['l1DMode',{desc:"L1D Cache",
55 base:0x11F04000,
56 map : [["0k",0x0000],
57 ["4k",0x1000],
58 ["8k",0x2000],
59 ["16k",0x4000],
60 ["32k",0x8000]],
61 defaultValue: "32k",
62 memorySection: "L1DSRAM"}],
63
64 ['l2Mode',{desc:"L2 Cache",
65 base:0x11800000,
66 map : [["0k",0x0000],
67 ["32k",0x8000],
68 ["64k",0x10000],
69 ["128k",0x20000]],
70 defaultValue: "0k",
71 memorySection: "IRAM"}],
72
73 ];
74
75 instance:
76
77 override config string cpuCore = "64x+";
78 override config string isa = "64P";
79 override config string cpuCoreRevision = "1.0";
80
81 override config int minProgUnitSize = 1;
82 override config int minDataUnitSize = 1;
83 override config int dataWordSize = 4;
84
85 /*!
86 * ======== memMap ========
87 * The default memory map for this device
88 */
89 config xdc.platform.IPlatform.Memory memMap[string] = [
90 ["IRAM", {
91 comment: "Internal 128KB UMAP0 memory",
92 name: "IRAM",
93 base: 0x11800000,
94 len: 0x00020000,
95 space: "code/data",
96 access: "RWX"
97 }],
98
99 ["L1PSRAM", {
100 comment: "Internal 32KB RAM/CACHE L1 program memory",
101 name: "L1PSRAM",
102 base: 0x11E08000,
103 len: 0x00008000,
104 space: "code",
105 access: "RWX"
106 }],
107
108 ["L1DSRAM", {
109 comment: "Internal 80KB RAM/CACHE L1 data memory",
110 name: "L1DSRAM",
111 base: 0x11F04000,
112 len: 0x00014000,
113 space: "data",
114 access: "RW"
115 }],
116
117 ["ARM_RAM", {
118 comment: "Internal ARM RAM memory",
119 name: "ARM_RAM",
120 base: 0x10008000,
121 len: 0x00004000,
122 space: "data",
123 access: "RW"
124 }],
125 ];
126 };
127 /*
128 * @(#) ti.catalog.c6000; 1, 0, 0, 0,295; 12-3-2010 11:44:01; /db/ztree/library/trees/platform/platform-l29x/src/
129 */
130