1 /*
2 * Copyright (c) 2010 by Texas Instruments and others.
3 * All rights reserved. This program and the accompanying materials
4 * are made available under the terms of the Eclipse Public License v1.0
5 * which accompanies this distribution, and is available at
6 * http://www.eclipse.org/legal/epl-v10.html
7 *
8 * Contributors:
9 * Texas Instruments - initial implementation
10 *
11 * */
12
13 /*
14 * ======== ITMS320CDM6467.xdc ========
15 *
16 */
17 package ti.catalog.c6000;
18
19 /*!
20 * ======== ITMS320CDM6467 ========
21 * An interface implemented by all DaVinci-HD devices
22 *
23 * This interface is defined to factor common data about all DaVinci-HD devices
24 * into a single place; they are all the same from the configuration point of
25 * view.
26 */
27 metaonly interface ITMS320CDM6467 inherits ti.catalog.ICpuDataSheet
28 {
29 config long cacheSizeL1[string] = [
30 ["0k", 0x0000],
31 ["4k", 0x1000],
32 ["8k", 0x2000],
33 ["16k", 0x4000],
34 ["32k", 0x8000],
35 ];
36
37 config long cacheSizeL2[string] = [
38 ["0k", 0x00000],
39 ["32k", 0x08000],
40 ["64k", 0x10000],
41 ["128k", 0x20000],
42 ];
43
44 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
45 ['l1PMode',{desc:"L1P Cache",
46 base:0x11E00000,
47 map : [["0k",0x0000],
48 ["4k",0x1000],
49 ["8k",0x2000],
50 ["16k",0x4000],
51 ["32k",0x8000]],
52 defaultValue: "32k",
53 memorySection: "L1PSRAM"}],
54
55 ['l1DMode',{desc:"L1D Cache",
56 base: 0x11F00000,
57 map : [["0k",0x0000],
58 ["4k",0x1000],
59 ["8k",0x2000],
60 ["16k",0x4000],
61 ["32k",0x8000]],
62 defaultValue: "32k",
63 memorySection: "L1DSRAM"}],
64
65 ['l2Mode',{desc:"L2 Cache",
66 base:0x11818000,
67 map : [["0k",0x0000],
68 ["32k",0x8000],
69 ["64k",0x10000],
70 ["128k",0x20000]],
71 defaultValue: "0k",
72 memorySection: "IRAM"}]
73
74 ];
75
76 instance:
77
78 override config string cpuCore = "64x+";
79 override config string isa = "64P";
80 override config string cpuCoreRevision = "1.0";
81
82 override config int minProgUnitSize = 1;
83 override config int minDataUnitSize = 1;
84 override config int dataWordSize = 4;
85
86 /*!
87 * ======== memMap ========
88 * The default memory map for this device
89 */
90 config xdc.platform.IPlatform.Memory memMap[string] = [
91 ["ARM_RAM", {
92 comment: "Internal ARM RAM memory",
93 name: "ARM_RAM",
94 base: 0x10010000,
95 len: 0x00008000,
96 space: "data",
97 access: "RW"
98 }],
99
100 ["IRAM", {
101 comment: "Internal 128KB UMAP0 memory",
102 name: "IRAM",
103 base: 0x11818000,
104 len: 0x00020000,
105 space: "code/data",
106 access: "RWX"
107 }],
108
109 ["L1PSRAM", {
110 comment: "Internal 32KB RAM/CACHE L1 program memory",
111 name: "L1PSRAM",
112 base: 0x11E00000,
113 len: 0x00008000,
114 space: "code",
115 access: "RWX"
116 }],
117
118 ["L1DSRAM", {
119 comment: "Internal 32KB RAM/CACHE L1 data memory",
120 name: "L1DSRAM",
121 base: 0x11F00000,
122 len: 0x00008000,
123 space: "data",
124 access: "RW"
125 }],
126 ];
127 };
128 /*
129 * @(#) ti.catalog.c6000; 1, 0, 0, 0,295; 12-3-2010 11:44:00; /db/ztree/library/trees/platform/platform-l29x/src/
130 */
131