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13 14 15 16
17 package ti.catalog.c6000;
18
19 /*!
20 * ======== ITMS320C6x1x ========
21 * An interface implemented by all TMS320C6x1x devices.
22 *
23 * This interface is defined to factor common data about this family into
24 * a single place; all TMS320C6x1x devices extend this interface.
25 */
26 metaonly interface ITMS320C6x1x inherits ti.catalog.ICpuDataSheet
27 {
28 config long cacheSize[string] = [
29 ["SRAM", 0x0000],
30 ["1-way cache", 0x4000],
31 ["2-way cache", 0x8000],
32 ["3-way cache", 0xc000],
33 ["4-way cache", 0x10000],
34 ["0k", 0x0000],
35 ["16k", 0x4000],
36 ["32k", 0x8000],
37 ["48k", 0xc000],
38 ["64k", 0x10000],
39 ];
40
41 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
42 ['l2Mode',{desc:"L2 Cache",
43 map : [["SRAM",0x0000],
44 ["1-way cache",0x4000],
45 ["2-way cache",0x8000],
46 ["3-way cache",0xc000],
47 ["4-way cache",0x10000]],
48 defaultValue: "4-way cache",
49 memorySection: "IRAM"}]
50 ];
51
52 instance:
53 override config string cpuCoreRevision = "1.0";
54
55 override config int minProgUnitSize = 1;
56 override config int minDataUnitSize = 1;
57 override config int dataWordSize = 4;
58
59 /*!
60 * ======== memMap ========
61 * The default memory map for this device
62 */
63 config xdc.platform.IPlatform.Memory memMap[string];
64 }
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68