1    /*
     2     *  Copyright (c) 2010 by Texas Instruments and others.
     3     *  All rights reserved. This program and the accompanying materials
     4     *  are made available under the terms of the Eclipse Public License v1.0
     5     *  which accompanies this distribution, and is available at
     6     *  http://www.eclipse.org/legal/epl-v10.html
     7     *
     8     *  Contributors:
     9     *      Texas Instruments - initial implementation
    10     *
    11     * */
    12    
    13    /*
    14     *  ======== ITMS320C64_512K.xdc ========
    15     *
    16     */
    17    package ti.catalog.c6000;
    18    
    19    /*!
    20     *  ======== ITMS320C64_512K ========
    21     *  An interface implemented by all TMS320C64xx devices with 512KB of internal
    22     *  memory.
    23     *
    24     *  This interface is defined to factor common data about this family into
    25     *  a single place; all TMS320C64xx devices with 512KB of internal
    26     *  memory extend this interface.
    27     */
    28    metaonly interface ITMS320C64_512K inherits ti.catalog.ICpuDataSheet
    29    {
    30    
    31        config long cacheSize[string] = [
    32            ["4-way cache (0k)",   0x00000],
    33            ["4-way cache (32k)",  0x08000],
    34            ["4-way cache (64k)",  0x10000],
    35            ["4-way cache (128k)", 0x20000],
    36            ["4-way cache (256k)", 0x40000],
    37            ["0k",   0x00000],
    38            ["32k",  0x08000],
    39            ["64k",  0x10000],
    40            ["128k", 0x20000],
    41            ["256k", 0x40000],
    42        ];
    43    
    44        readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] =  [
    45             ['l2Mode',{desc:"L2 Cache",
    46                         map : [["4-way cache (0k)",0x0000],
    47                                ["4-way cache (32k)",0x8000],
    48                                ["4-way cache (64k)",0x10000],
    49                                ["4-way cache (128k)",0x20000],
    50                                ["4-way cache (256k)",0x40000]],
    51                         defaultValue: "4-way cache (0k)",
    52                         memorySection: "IRAM"}]
    53        ];
    54    
    55    instance:
    56        override config int     minProgUnitSize = 1;
    57        override config int     minDataUnitSize = 1;    
    58        override config int     dataWordSize    = 4;
    59        
    60        override config string   cpuCore        = "6400";
    61        override config string   isa="64";
    62        override config string   cpuCoreRevision = "1.0";
    63    
    64        /*!
    65         *  ======== memMap ========
    66         *  The default memory map for this device
    67         */
    68        config xdc.platform.IPlatform.Memory memMap[string]  = [
    69            ["IRAM", {
    70                name:       "IRAM",
    71                comment:    "Internal L2 memory",
    72                base:       0x00000,
    73                len:        0x80000,
    74                space:      "code/data",
    75                access:     "RWX"
    76            }],
    77        ];
    78    }
    79    /*
    80     *  @(#) ti.catalog.c6000; 1, 0, 0, 0,295; 12-3-2010 11:44:00; /db/ztree/library/trees/platform/platform-l29x/src/
    81     */
    82