1 /*
2 * Copyright (c) 2010 by Texas Instruments and others.
3 * All rights reserved. This program and the accompanying materials
4 * are made available under the terms of the Eclipse Public License v1.0
5 * which accompanies this distribution, and is available at
6 * http://www.eclipse.org/legal/epl-v10.html
7 *
8 * Contributors:
9 * Texas Instruments - initial implementation
10 *
11 * */
12
13 /*
14 * ======== ITMS320C6452.xdc ========
15 *
16 */
17 package ti.catalog.c6000;
18
19 /*!
20 * ======== ITMS320C6452 ========
21 * The interface for 6452 and similar devices' data sheet module.
22 *
23 * This module implements the ICpuDataSheet interface and is
24 * used by platforms to obtain "data sheet" information about this device.
25 */
26 metaonly interface ITMS320C6452 inherits ti.catalog.ICpuDataSheet
27 {
28
29 config long cacheSizeL1[string] = [
30 ["0k", 0x0000],
31 ["4k", 0x1000],
32 ["8k", 0x2000],
33 ["16k", 0x4000],
34 ["32k", 0x8000],
35 ];
36
37 config long cacheSizeL2[string] = [
38 ["0k", 0x00000],
39 ["32k", 0x08000],
40 ["64k", 0x10000],
41 ["128k", 0x20000],
42 ["256k", 0x40000]
43 ];
44
45 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
46 ['l1PMode',{desc:"L1P Cache",
47 base:0xE00000,
48 map : [["0k",0x0000],
49 ["4k",0x1000],
50 ["8k",0x2000],
51 ["16k",0x4000],
52 ["32k",0x8000]],
53 defaultValue: "32k",
54 memorySection: "L1PSRAM"}],
55
56 ['l1DMode',{desc:"L1D Cache",
57 base:0xF00000,
58 map : [["0k",0x0000],
59 ["4k",0x1000],
60 ["8k",0x2000],
61 ["16k",0x4000],
62 ["32k",0x8000]],
63 defaultValue: "32k",
64 memorySection: "L1DSRAM"}],
65
66 ['l2Mode',{desc:"L2 Cache",
67 base:0xA00000,
68 map : [["0k",0x0000],
69 ["32k",0x8000],
70 ["64k",0x10000],
71 ["128k",0x20000],
72 ["256k",0x40000]],
73 defaultValue: "0k",
74 memorySection: "IRAM"}],
75 ];
76
77 instance:
78
79 override config string cpuCore = "64x+";
80 override config string isa = "64P";
81 override config string cpuCoreRevision = "1.0";
82
83 override config int minProgUnitSize = 1;
84 override config int minDataUnitSize = 1;
85 override config int dataWordSize = 4;
86
87 /*!
88 * ======== memMap ========
89 * The default memory map for this device
90 */
91 config xdc.platform.IPlatform.Memory memMap[string] = [
92 ["IRAM", {
93 comment: "Internal 1408KB L2 RAM/CACHE",
94 name: "IRAM",
95 base: 0xA00000,
96 len: 0x160000,
97 space: "code/data",
98 access: "RWX"
99 }],
100
101 ["L1PSRAM", {
102 comment: "Internal 32KB RAM/CACHE L1 program memory",
103 name: "L1PSRAM",
104 base: 0xE00000,
105 len: 0x008000,
106 space: "code",
107 access: "RWX"
108 }],
109
110 ["L1DSRAM", {
111 comment: "Internal 32KB RAM/CACHE L1 data memory",
112 name: "L1DSRAM",
113 base: 0xF00000,
114 len: 0x008000,
115 space: "data",
116 access: "RW"
117 }],
118
119 ];
120 };
121 /*
122 * @(#) ti.catalog.c6000; 1, 0, 0, 0,295; 12-3-2010 11:43:59; /db/ztree/library/trees/platform/platform-l29x/src/
123 */
124