1 /*
2 * Copyright (c) 2010 by Texas Instruments and others.
3 * All rights reserved. This program and the accompanying materials
4 * are made available under the terms of the Eclipse Public License v1.0
5 * which accompanies this distribution, and is available at
6 * http://www.eclipse.org/legal/epl-v10.html
7 *
8 * Contributors:
9 * Texas Instruments - initial implementation
10 *
11 * */
12
13 /*
14 * ======== ITI8148.xdc ========
15 *
16 */
17 package ti.catalog.c6000;
18
19 /*!
20 * ======== ITI8148 ========
21 * An interface implemented by all TI8148 devices
22 *
23 * This interface is defined to factor common data about all TI8148 type devices
24 * into a single place; they all have the same internal memory.
25 */
26 metaonly interface ITI8148 inherits ti.catalog.ICpuDataSheet
27 {
28
29 config long cacheSizeL1[string] = [
30 ["0k", 0x0000],
31 ["4k", 0x1000],
32 ["8k", 0x2000],
33 ["16k", 0x4000],
34 ["32k", 0x8000],
35 ];
36
37 config long cacheSizeL2[string] = [
38 ["0k", 0x00000],
39 ["32k", 0x08000],
40 ["64k", 0x10000],
41 ["128k",0x20000],
42 ["256k",0x40000],
43 ];
44
45 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
46 ['l1PMode',{desc:"L1P Cache",
47 base:0x10E00000,
48 map : [["0k",0x0000],
49 ["4k",0x1000],
50 ["8k",0x2000],
51 ["16k",0x4000],
52 ["32k",0x8000]],
53 defaultValue: "32k",
54 memorySection: "L1PSRAM"}],
55
56 ['l1DMode',{desc:"L1D Cache",
57 base:0x10F00000,
58 map : [["0k",0x0000],
59 ["4k",0x1000],
60 ["8k",0x2000],
61 ["16k",0x4000],
62 ["32k",0x8000]],
63 defaultValue: "32k",
64 memorySection: "L1DSRAM"}],
65
66 ['l2Mode',{desc:"L2 Cache",
67 base:0x10800000,
68 map : [["0k",0x0000],
69 ["32k",0x8000],
70 ["64k",0x10000],
71 ["128k",0x20000],
72 ["256k",0x40000]],
73 defaultValue: "0k",
74 memorySection: "IRAM"}],
75
76 ];
77
78 instance:
79 config ti.catalog.peripherals.hdvicp2.HDVICP2.Instance hdvicp0;
80
81 override config int minProgUnitSize = 1;
82 override config int minDataUnitSize = 1;
83 override config int dataWordSize = 4;
84
85 override config string cpuCore = "674";
86 override config string isa = "674";
87 override config string cpuCoreRevision = "1.0";
88
89 config xdc.platform.IPlatform.Memory memMap[string] = [
90
91 ["IRAM", {
92 comment: "Internal 256KB L2 memory",
93 name: "IRAM",
94 base: 0x10800000,
95 len: 0x00040000,
96 space: "code/data",
97 access: "RWX"
98 }],
99
100 ["L1PSRAM", {
101 comment: "Internal 32KB L1 program memory",
102 name: "L1PSRAM",
103 base: 0x10E00000,
104 len: 0x00008000,
105 space: "code",
106 access: "RWX"
107 }],
108
109 ["L1DSRAM", {
110 comment: "Internal 32KB L1 data memory",
111 name: "L1DSRAM",
112 base: 0x10F00000,
113 len: 0x00008000,
114 space: "data",
115 access: "RW"
116 }],
117
118 ["OCMC_0", {
119 comment: "OCMC (On-chip RAM) Bank 0 (128KB)",
120 name: "OCMC_0",
121 base: 0x40300000,
122 len: 0x00020000,
123 space: "code/data",
124 access: "RWX"
125 }],
126
127 ["OCMC_1", {
128 comment: "OCMC (On-chip RAM) Bank 1 (128KB)",
129 name: "OCMC_1",
130 base: 0x40400000,
131 len: 0x00020000,
132 space: "code/data",
133 access: "RWX"
134 }],
135 ];
136 };
137 /*
138 * @(#) ti.catalog.c6000; 1, 0, 0, 0,295; 12-3-2010 11:43:59; /db/ztree/library/trees/platform/platform-l29x/src/
139 */
140