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17 package ti.catalog.c6000;
18
19 /*!
20 * ======== IOMAP2x3x ========
21 * An interface implemented by all OMAP2x3x devices
22 *
23 * This interface is defined to factor common data about all OMAP2x3x devices
24 * into a single place; they all have the same internal memory.
25 */
26 metaonly interface IOMAP2x3x inherits ti.catalog.ICpuDataSheet
27 {
28
29 config long cacheSizeL1[string] = [
30 ["0k", 0x0000],
31 ["4k", 0x1000],
32 ["8k", 0x2000],
33 ["16k", 0x4000],
34 ["32k", 0x8000],
35 ];
36
37 config long cacheSizeL2[string] = [
38 ["0k", 0x00000],
39 ["32k", 0x08000],
40 ["64k", 0x10000]
41 ];
42
43 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
44 ['l1PMode',{desc:"L1P Cache",
45 base:0x10E00000,
46 map : [["0k",0x0000],
47 ["4k",0x1000],
48 ["8k",0x2000],
49 ["16k",0x4000],
50 ["32k",0x8000]],
51 defaultValue: "32k",
52 memorySection: "L1PSRAM"}],
53
54 ['l1DMode',{desc:"L1D Cache",
55 base:0x10F04000,
56 map : [["0k",0x0000],
57 ["4k",0x1000],
58 ["8k",0x2000],
59 ["16k",0x4000],
60 ["32k",0x8000]],
61 defaultValue: "32k",
62 memorySection: "L1DSRAM"}],
63
64 ['l2Mode',{desc:"L2 Cache",
65 base: 0x10800000,
66 map : [["0k",0x0000],
67 ["32k",0x8000],
68 ["64k",0x10000]],
69 defaultValue: "0k",
70 memorySection: "IRAM"}],
71
72 ];
73
74 instance:
75 override config int minProgUnitSize = 1;
76 override config int minDataUnitSize = 1;
77 override config int dataWordSize = 4;
78
79 override config string cpuCore = "64x+";
80 override config string isa = "64P";
81
82 config xdc.platform.IPlatform.Memory memMap[string] = [
83 ["IRAM", {
84 comment: "Internal 64KB L2 UMAP0 memory",
85 name: "IRAM",
86 base: 0x10800000,
87 len: 0x00010000,
88 space: "code/data",
89 access: "RWX"
90 }],
91
92 ["L1PSRAM", {
93 comment: "Internal 32KB L1 program memory",
94 name: "L1PSRAM",
95 base: 0x10E00000,
96 len: 0x00008000,
97 space: "code",
98 access: "RWX"
99 }],
100
101 ["L1DSRAM", {
102 comment: "Internal 80KB L1 data memory",
103 name: "L1DSRAM",
104 base: 0x10F04000,
105 len: 0x00014000,
106 space: "data",
107 access: "RW"
108 }],
109 ];
110 };
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