1 /*
2 * Copyright (c) 2010 by Texas Instruments and others.
3 * All rights reserved. This program and the accompanying materials
4 * are made available under the terms of the Eclipse Public License v1.0
5 * which accompanies this distribution, and is available at
6 * http://www.eclipse.org/legal/epl-v10.html
7 *
8 * Contributors:
9 * Texas Instruments - initial implementation
10 *
11 * */
12
13 /*
14 * ======== Arctic.xdc ========
15 *
16 */
17
18 /*!
19 * ======== Arctic ========
20 * The Arctic device data sheet module.
21 *
22 * This module implements the ICpuDataSheet interface and is
23 * used by platforms to obtain "data sheet" information about this device.
24 */
25 metaonly module Arctic inherits ti.catalog.ICpuDataSheet
26 {
27 config long cacheSizeL1[string] = [
28 ["0k", 0x0000],
29 ["4k", 0x1000],
30 ["8k", 0x2000],
31 ["16k", 0x4000],
32 ["32k", 0x8000],
33 ];
34
35 config long cacheSizeL2[string] = [
36 ["0k", 0x00000],
37 ["32k", 0x08000],
38 ["64k", 0x10000],
39 ["128k", 0x20000],
40 ["256k", 0x40000],
41 ["512k", 0x80000],
42 ];
43
44 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
45 ['l1PMode',{desc:"L1P Cache",
46 base: 0xE00000,
47 map : [["0k",0x0000],
48 ["4k",0x1000],
49 ["8k",0x2000],
50 ["16k",0x4000],
51 ["32k",0x8000]],
52 defaultValue: "32k",
53 memorySection: "L1PSRAM"}],
54
55 ['l1DMode',{desc:"L1D Cache",
56 base: 0xF00000,
57 map : [["0k",0x0000],
58 ["4k",0x1000],
59 ["8k",0x2000],
60 ["16k",0x4000],
61 ["32k",0x8000]],
62 defaultValue: "32k",
63 memorySection: "L1DSRAM"}],
64
65 ['l2Mode',{desc:"L2 Cache",
66 base: 0x800000,
67 map : [["0k",0x0000],
68 ["32k",0x8000],
69 ["64k",0x10000],
70 ["128k",0x20000],
71 ["256k",0x40000],
72 ["512k",0x80000]],
73 defaultValue: "0k",
74 memorySection: "IRAM"}],
75 ];
76
77 instance:
78
79 override config string cpuCore = "C674";
80 override config string isa = "674";
81 override config string cpuCoreRevision = "1.0";
82
83 override config int minProgUnitSize = 1;
84 override config int minDataUnitSize = 1;
85 override config int dataWordSize = 4;
86
87 /*!
88 * ======== memMap ========
89 * The default memory map for this device
90 */
91 config xdc.platform.IPlatform.Memory memMap[string] = [
92 ["IRAM", {
93 comment: "Internal 512KB L2 RAM/cache memory",
94 name: "IRAM",
95 base: 0x00800000,
96 len: 0x00080000,
97 space: "code/data",
98 access: "RWX"
99 }],
100
101 ["L1PSRAM", {
102 comment: "Internal 32KB L1 program/cache memory",
103 name: "L1PSRAM",
104 base: 0x00E00000,
105 len: 0x00008000,
106 space: "code",
107 access: "RX"
108 }],
109
110 ["L1DSRAM", {
111 comment: "Internal 32KB L1 data/cache memory",
112 name: "L1DSRAM",
113 base: 0x00F00000,
114 len: 0x00008000,
115 space: "data",
116 access: "RW"
117 }],
118
119 ["L3MEM", {
120 comment: "1MB L3 Memory",
121 name: "L3MEM",
122 base: 0x7FF00000,
123 len: 0x00100000,
124 space: "code/data",
125 access: "RWX"
126 }],
127
128 /*
129 * This memory needs to be defined here as a workaround because
130 * IPC generates a section that needs to be placed here. Once
131 * we fix the enhancement SDOCM00077090 in IPC, this can be removed.
132 */
133 ["DMEM", {
134 comment: "T16 Internal data memory",
135 name: "DMEM",
136 base: 0x20020000,
137 len: 0x8000,
138 space: "data",
139 access: "RW"
140 }],
141 ];
142 };
143 /*
144 * @(#) ti.catalog.c6000; 1, 0, 0, 0,295; 12-3-2010 11:43:47; /db/ztree/library/trees/platform/platform-l29x/src/
145 */
146