1 /*! 2 * ======== Timer_B7 ======== 3 * MSP430 Timer_B7 timer 4 */ 5 metaonly module Timer_B7 inherits ITimer_B { 6 7 /*! TB7IV Definitions */ 8 enum IVValues { 9 TBIV_NONE = 0x0000, /*! No Interrupt pending */ 10 TBIV_TBCCR1 = 0x0002, /*! TBCCR1_CCIFG */ 11 TBIV_TBCCR2 = 0x0004, /*! TBCCR2_CCIFG */ 12 TBIV_TBCCR3 = 0x0006, /*! TBCCR3_CCIFG */ 13 TBIV_TBCCR4 = 0x0008, /*! TBCCR4_CCIFG */ 14 TBIV_TBCCR5 = 0x000A, /*! TBCCR5_CCIFG */ 15 TBIV_TBCCR6 = 0x000C, /*! TBCCR6_CCIFG */ 16 TBIV_TBIFG = 0x000E /*! TBIFG */ 17 }; 18 19 instance: 20 /*! TBCTL, Timer_B7 Control Register */ 21 config TBCTL_t TBCTL = { 22 TBCLGRP : TBCLGRP_0, 23 CNTL : CNTL_0, 24 TBSSEL : TBSSEL_0, 25 ID : ID_0, 26 MC : MC_0, 27 TBCLR : TBCLR_OFF, 28 TBIE : TBIE_OFF, 29 TBIFG : TBIFG_OFF 30 }; 31 32 /*! TBCCTL0, Capture/Compare Control Register 0 */ 33 config TBCCTLx_t TBCCTL0 = { 34 CM : CM_0, 35 CCIS : CCIS_0, 36 SCS : SCS_OFF, 37 CLLD : CLLD_0, 38 CAP : CAP_OFF, 39 OUTMOD : OUTMOD_0, 40 CCIE : CCIE_OFF, 41 CCI : CCI_OFF, 42 OUT : OUT_OFF, 43 COV : COV_OFF, 44 CCIFG : CCIFG_OFF 45 }; 46 47 /*! TBCCTL1, Capture/Compare Control Register 1 */ 48 config TBCCTLx_t TBCCTL1 = { 49 CM : CM_0, 50 CCIS : CCIS_0, 51 SCS : SCS_OFF, 52 CLLD : CLLD_0, 53 CAP : CAP_OFF, 54 OUTMOD : OUTMOD_0, 55 CCIE : CCIE_OFF, 56 CCI : CCI_OFF, 57 OUT : OUT_OFF, 58 COV : COV_OFF, 59 CCIFG : CCIFG_OFF 60 }; 61 62 /*! TBCCTL2, Capture/Compare Control Register 2 */ 63 config TBCCTLx_t TBCCTL2 = { 64 CM : CM_0, 65 CCIS : CCIS_0, 66 SCS : SCS_OFF, 67 CLLD : CLLD_0, 68 CAP : CAP_OFF, 69 OUTMOD : OUTMOD_0, 70 CCIE : CCIE_OFF, 71 CCI : CCI_OFF, 72 OUT : OUT_OFF, 73 COV : COV_OFF, 74 CCIFG : CCIFG_OFF 75 }; 76 77 /*! TBCCTL3, Capture/Compare Control Register 3 */ 78 config TBCCTLx_t TBCCTL3 = { 79 CM : CM_0, 80 CCIS : CCIS_0, 81 SCS : SCS_OFF, 82 CLLD : CLLD_0, 83 CAP : CAP_OFF, 84 OUTMOD : OUTMOD_0, 85 CCIE : CCIE_OFF, 86 CCI : CCI_OFF, 87 OUT : OUT_OFF, 88 COV : COV_OFF, 89 CCIFG : CCIFG_OFF 90 }; 91 92 /*! TBCCTL4, Capture/Compare Control Register 4 */ 93 config TBCCTLx_t TBCCTL4 = { 94 CM : CM_0, 95 CCIS : CCIS_0, 96 SCS : SCS_OFF, 97 CLLD : CLLD_0, 98 CAP : CAP_OFF, 99 OUTMOD : OUTMOD_0, 100 CCIE : CCIE_OFF, 101 CCI : CCI_OFF, 102 OUT : OUT_OFF, 103 COV : COV_OFF, 104 CCIFG : CCIFG_OFF 105 }; 106 107 /*! TBCCTL5, Capture/Compare Control Register 5 */ 108 config TBCCTLx_t TBCCTL5 = { 109 CM : CM_0, 110 CCIS : CCIS_0, 111 SCS : SCS_OFF, 112 CLLD : CLLD_0, 113 CAP : CAP_OFF, 114 OUTMOD : OUTMOD_0, 115 CCIE : CCIE_OFF, 116 CCI : CCI_OFF, 117 OUT : OUT_OFF, 118 COV : COV_OFF, 119 CCIFG : CCIFG_OFF 120 }; 121 122 /*! TBCCTL6, Capture/Compare Control Register 6 */ 123 config TBCCTLx_t TBCCTL6 = { 124 CM : CM_0, 125 CCIS : CCIS_0, 126 SCS : SCS_OFF, 127 CLLD : CLLD_0, 128 CAP : CAP_OFF, 129 OUTMOD : OUTMOD_0, 130 CCIE : CCIE_OFF, 131 CCI : CCI_OFF, 132 OUT : OUT_OFF, 133 COV : COV_OFF, 134 CCIFG : CCIFG_OFF 135 }; 136 137 /*! TBCCR0, Timer_B Capture/Compare Register 0 */ 138 config int TBCCR0 = 0; 139 /*! TBCCR1, Timer_B Capture/Compare Register 1 */ 140 config int TBCCR1 = 0; 141 /*! TBCCR2, Timer_B Capture/Compare Register 2 */ 142 config int TBCCR2 = 0; 143 /*! TBCCR3, Timer_B Capture/Compare Register 3 */ 144 config int TBCCR3 = 0; 145 /*! TBCCR4, Timer_B Capture/Compare Register 4 */ 146 config int TBCCR4 = 0; 147 /*! TBCCR5, Timer_B Capture/Compare Register 5 */ 148 config int TBCCR5 = 0; 149 /*! TBCCR6, Timer_B Capture/Compare Register 6 */ 150 config int TBCCR6 = 0; 151 152 /*! Determine if each Register needs to be forced set or not */ 153 readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] = 154 [ 155 { register : "TBCTL" , regForceSet : false }, 156 { register : "TBCCTL0" , regForceSet : false }, 157 { register : "TBCCTL1" , regForceSet : false }, 158 { register : "TBCCTL2" , regForceSet : false }, 159 { register : "TBCCTL3" , regForceSet : false }, 160 { register : "TBCCTL4" , regForceSet : false }, 161 { register : "TBCCTL5" , regForceSet : false }, 162 { register : "TBCCTL6" , regForceSet : false }, 163 { register : "TBCCR0" , regForceSet : false }, 164 { register : "TBCCR1" , regForceSet : false }, 165 { register : "TBCCR2" , regForceSet : false }, 166 { register : "TBCCR3" , regForceSet : false }, 167 { register : "TBCCR4" , regForceSet : false }, 168 { register : "TBCCR5" , regForceSet : false }, 169 { register : "TBCCR6" , regForceSet : false } 170 ]; 171 }