1 /*! 2 * ======== Timer_B3 ======== 3 * MSP430 Timer_B timer 4 */ 5 metaonly module Timer_B3 inherits ITimer_B { 6 7 /*! TB3IV Definitions */ 8 enum IVValues { 9 TBIV_NONE = 0x0000, /*! No Interrupt pending */ 10 TBIV_TBCCR1 = 0x0002, /*! TBCCR1_CCIFG */ 11 TBIV_TBCCR2 = 0x0004, /*! TBCCR2_CCIFG */ 12 TBIV_6 = 0x0006, /*! Reserved */ 13 TBIV_8 = 0x0008, /*! Reserved */ 14 TBIV_TBIFG = 0x000A /*! TBIFG */ 15 }; 16 17 instance: 18 /*! TBCTL, Timer_B3 Control Register */ 19 config TBCTL_t TBCTL = { 20 TBCLGRP : TBCLGRP_0, 21 CNTL : CNTL_0, 22 TBSSEL : TBSSEL_0, 23 ID : ID_0, 24 MC : MC_0, 25 TBCLR : TBCLR_OFF, 26 TBIE : TBIE_OFF, 27 TBIFG : TBIFG_OFF 28 }; 29 30 /*! TBCCTL0, Capture/Compare Control Register 0 */ 31 config TBCCTLx_t TBCCTL0 = { 32 CM : CM_0, 33 CCIS : CCIS_0, 34 SCS : SCS_OFF, 35 CLLD : CLLD_0, 36 CAP : CAP_OFF, 37 OUTMOD : OUTMOD_0, 38 CCIE : CCIE_OFF, 39 CCI : CCI_OFF, 40 OUT : OUT_OFF, 41 COV : COV_OFF, 42 CCIFG : CCIFG_OFF 43 }; 44 45 /*! TBCCTL1, Capture/Compare Control Register 1 */ 46 config TBCCTLx_t TBCCTL1 = { 47 CM : CM_0, 48 CCIS : CCIS_0, 49 SCS : SCS_OFF, 50 CLLD : CLLD_0, 51 CAP : CAP_OFF, 52 OUTMOD : OUTMOD_0, 53 CCIE : CCIE_OFF, 54 CCI : CCI_OFF, 55 OUT : OUT_OFF, 56 COV : COV_OFF, 57 CCIFG : CCIFG_OFF 58 }; 59 60 /*! TBCCTL2, Capture/Compare Control Register 2 */ 61 config TBCCTLx_t TBCCTL2 = { 62 CM : CM_0, 63 CCIS : CCIS_0, 64 SCS : SCS_OFF, 65 CLLD : CLLD_0, 66 CAP : CAP_OFF, 67 OUTMOD : OUTMOD_0, 68 CCIE : CCIE_OFF, 69 CCI : CCI_OFF, 70 OUT : OUT_OFF, 71 COV : COV_OFF, 72 CCIFG : CCIFG_OFF 73 }; 74 75 /*! TBCCR0, Timer_B Capture/Compare Register 0 */ 76 config int TBCCR0 = 0; 77 /*! TBCCR1, Timer_B Capture/Compare Register 1 */ 78 config int TBCCR1 = 0; 79 /*! TBCCR2, Timer_B Capture/Compare Register 2 */ 80 config int TBCCR2 = 0; 81 82 /*! Determine if each Register needs to be forced set or not */ 83 readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] = 84 [ 85 { register : "TBCTL" , regForceSet : false }, 86 { register : "TBCCTL0" , regForceSet : false }, 87 { register : "TBCCTL1" , regForceSet : false }, 88 { register : "TBCCTL2" , regForceSet : false }, 89 { register : "TBCCR0" , regForceSet : false }, 90 { register : "TBCCR1" , regForceSet : false }, 91 { register : "TBCCR2" , regForceSet : false } 92 ]; 93 }