1 import ti.catalog.msp430.peripherals.clock.IClock;
2
3
4 /*!
5 * ======== ITimer_A ========
6 * MSP430 ITimer_A interface
7 */
8 metaonly interface ITimer_A inherits xdc.platform.IPeripheral {
9
10 enum TASSEL_t {
11 TASSEL_0 = (0*0x100u), /*! TACLK */
12 TASSEL_1 = (1*0x100u), /*! ACLK */
13 TASSEL_2 = (2*0x100u), /*! SMCLK */
14 TASSEL_3 = 3*0x100u /*! INCLK */
15 };
16
17 enum TACLR_t {
18 TACLR_OFF = (0x0000),
19 TACLR = 0x0004
20 };
21
22 enum TAIE_t {
23 TAIE_OFF = (0x0000),
24 TAIE = 0x0002
25 };
26
27 enum TAIFG_t {
28 TAIFG_OFF = (0x000),
29 TAIFG = (0x0001)
30 };
31
32 enum MC_t {
33 MC_0 = (0*0x10u), /*! Stop Mode */
34 MC_1 = (1*0x10u), /*! Up Mode */
35 MC_2 = (2*0x10u), /*! Continuous Mode */
36 MC_3 = 3*0x10u /*! Up/Down Mode */
37 };
38
39 enum ID_t {
40 ID_0 = (0*0x40u), /*! Divider - /1 */
41 ID_1 = (1*0x40u), /*! Divider - /2 */
42 ID_2 = (2*0x40u), /*! Divider - /4 */
43 ID_3 = 3*0x40u /*! Divider - /8 */
44 };
45
46 enum CM_t {
47 CM_0 = (0*0x4000u), /*! No Capture */
48 CM_1 = (1*0x4000u), /*! Rising Edge */
49 CM_2 = (2*0x4000u), /*! Falling Edge */
50 CM_3 = 3*0x4000u /*! Both Edges */
51 };
52
53 enum CCIS_t {
54 CCIS_0 = (0*0x1000u), /*! CCIxA */
55 CCIS_1 = (1*0x1000u), /*! CCIxB */
56 CCIS_2 = (2*0x1000u), /*! GND */
57 CCIS_3 = 3*0x1000u /*! Vcc */
58 };
59
60 enum SCS_t {
61 SCS_OFF = (0x0000), /*! Asynchronous Capture */
62 SCS = 0x0800 /*! Sychronous Capture */
63 };
64
65 enum SCCI_t {
66 SCCI_OFF = (0x0000), /*! Latched capture signal (read) */
67 SCCI = 0x0400 /*! Latched capture signal (read) */
68 };
69
70 enum CAP_t {
71 CAP_OFF = (0x0000), /*! Compare mode */
72 CAP = 0x0100 /*! Capture mode */
73 };
74
75 enum CCIE_t {
76 CCIE_OFF = (0x0000),
77 CCIE = (0x0010)
78 };
79
80 enum CCI_t {
81 CCI_OFF = (0x0008),
82 CCI = (0x0008)
83 };
84
85 enum OUT_t {
86 OUT_OFF = (0x0000),
87 OUT = (0x0004)
88 };
89
90 enum COV_t {
91 COV_OFF = (0x0000),
92 COV = (0x0002)
93 };
94
95 enum CCIFG_t {
96 CCIFG_OFF = (0x0000),
97 CCIFG = (0x0001)
98 };
99
100 enum OUTMOD_t {
101 OUTMOD_0 = (0*0x20u), /*! PWM output mode: 0 - OUT bit value */
102 OUTMOD_1 = (1*0x20u), /*! PWM output mode: 1 - Set */
103 OUTMOD_2 = (2*0x20u), /*! PWM output mode: 2 - PWM toggle/reset */
104 OUTMOD_3 = (3*0x20u), /*! PWM output mode: 3 - PWM set/reset */
105 OUTMOD_4 = (4*0x20u), /*! PWM output mode: 4 - Toggle */
106 OUTMOD_5 = (5*0x20u), /*! PWM output mode: 5 - Reset */
107 OUTMOD_6 = (6*0x20u), /*! PWM output mode: 6 - PWM toggle/set */
108 OUTMOD_7 = 7*0x20u /*! PWM output mode: 7 - PWM reset/set */
109 };
110
111 /*! TA3IV Definitions */
112 enum IVValues {
113 TAIV_NONE = 0x0000, /*! No Interrupt pending */
114 TAIV_TACCR1 = 0x0002, /*! TACCR1_CCIFG */
115 TAIV_TACCR2 = 0x0004, /*! TACCR2_CCIFG */
116 TAIV_6 = 0x0006, /*! Reserved */
117 TAIV_8 = 0x0008, /*! Reserved */
118 TAIV_TAIFG = 0x000A /*! TAIFG */
119 };
120
121 /*!
122 * ======== TACTL_t ========
123 * Timer_A Control Register
124 *
125 * @see #TACTL_t
126 */
127 struct TACTL_t {
128 TASSEL_t TASSEL; /*! Timer_A clock source select
129 * 00 TACLK
130 * 01 ACLK
131 * 10 SMCLK
132 * 11 INCLK */
133 ID_t ID; /*! Input divider. These bits select the divider for the input clock.
134 * 00 /1
135 * 01 /2
136 * 10 /4
137 * 11 /8 */
138 MC_t MC; /*! Mode control. Setting MCx = 00h when Timer_A is not in use conserves
139 * power.
140 * 00 Stop mode: the timer is halted.
141 * 01 Up mode: the timer counts up to TACCR0.
142 * 10 Continuous mode: the timer counts up to 0FFFFh.
143 * 11 Up/down mode: the timer counts up to TACCR0 then down to 0000h. */
144 TACLR_t TACLR; /*! Timer_A clear. Setting this bit resets TAR, the clock divider, and the count
145 * direction. The TACLR bit is automatically reset and is always read as zero. */
146 TAIE_t TAIE; /*! Timer_A interrupt enable. This bit enables the TAIFG interrupt request.
147 * 0 Interrupt disabled
148 * 1 Interrupt enabled */
149 TAIFG_t TAIFG; /*! Timer_A interrupt flag
150 * 0 No interrupt pending
151 * 1 Interrupt pending */
152 }
153
154 /*!
155 * ======== TACCTLx_t ========
156 * Capture/Compare Control Register
157 *
158 * @see #TACCTLx_t
159 */
160 struct TACCTLx_t {
161 CM_t CM; /*! Capture mode
162 * 00 No capture
163 * 01 Capture on rising edge
164 * 10 Capture on falling edge
165 * 11 Capture on both rising and falling edges */
166 CCIS_t CCIS; /*! Capture/compare input select. These bits select the TACCRx input signal.
167 * See the device-specific data sheet for specific signal connections.
168 * 00 CCIxA
169 * 01 CCIxB
170 * 10 GND
171 * 11 VCC */
172 SCS_t SCS; /*! Synchronize capture source. This bit is used to synchronize the capture input
173 * signal with the timer clock.
174 * 0 Asynchronous capture
175 * 1 Synchronous capture */
176 SCCI_t SCCI; /*! Synchronized capture/compare input. The selected CCI input signal is
177 * latched with the EQUx signal and can be read via this bit */
178 CAP_t CAP; /*! Capture mode
179 * 0 Compare mode
180 * 1 Capture mode */
181 OUTMOD_t OUTMOD; /*! Output mode. Modes 2, 3, 6, and 7 are not useful for TACCR0 because
182 * EQUx = EQU0.
183 * 000 OUT bit value
184 * 001 Set
185 * 010 Toggle/reset
186 * 011 Set/reset
187 * 100 Toggle
188 * 101 Reset
189 * 110 Toggle/set
190 * 111 Reset/set */
191 CCIE_t CCIE; /*! Capture/compare interrupt enable. This bit enables the interrupt request of
192 * the corresponding CCIFG flag.
193 * 0 Interrupt disabled
194 * 1 Interrupt enabled */
195 CCI_t CCI; /*! Capture/compare input. The selected input signal can be read by this bit. */
196 OUT_t OUT; /*! Output. For output mode 0, this bit directly controls the state of the output.
197 * 0 Output low
198 * 1 Output high */
199 COV_t COV; /*! Capture overflow. This bit indicates a capture overflow occurred. COV must
200 * be reset with software.
201 * 0 No capture overflow occurred
202 * 1 Capture overflow occurred */
203 CCIFG_t CCIFG; /*! Capture/compare interrupt flag
204 * 0 No interrupt pending
205 * 1 Interrupt pending */
206 }
207
208 /*!
209 * ======== ForceSetDefaultRegister_t ========
210 * Force Set Default Register
211 *
212 * Type to store if each register needs to be forced initialized
213 * even if the register is in default state.
214 *
215 * @see #ForceSetDefaultRegister_t
216 */
217 struct ForceSetDefaultRegister_t {
218 String register;
219 Bool regForceSet;
220 }
221
222 create(IClock.Instance clock);
223
224 instance:
225 /*!
226 * ======== baseAddr ========
227 * Address of the peripheral's control register.
228 *
229 * A peripheral's registers are commonly accessed through a structure
230 * that defines the offsets of a particular register from the lowest
231 * address mapped to a peripheral. That lowest address is specified by
232 * this parameter.
233 */
234 config UInt baseAddr;
235
236 /*!
237 * ======== intNum ========
238 * Interrupt source number
239 *
240 */
241 config UInt intNum;
242
243 /*! Timer_A TACLK */
244 config float TACLK = 0;
245
246 /*! Timer_A INCLK */
247 config float INCLK = 0;
248
249 /*! @_nodoc */
250 config IClock.Instance clock;
251
252
253 UChar getNumberOfTimers();
254 }