1 import ti.catalog.msp430.peripherals.clock.IClock;
2 import ti.catalog.msp430.peripherals.special_function.IE2;
3
4 /*!
5 * Universal Serial Communication Interface A0 UART 2xx
6 */
7 metaonly module USCI_A0_UART_2xx inherits IUSCI_A0_UART {
8
9
10 11 12
13 create(IClock.Instance clock , IE2.Instance interruptEnableRegister2);
14
15 instance:
16 /*! @_nodoc */
17 config IClock.Instance clock;
18 /*! @_nodoc */
19 config IE2.Instance interruptEnableRegister2;
20
21 /*! Determine if each Register needs to be forced set or not */
22 readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
23 [
24 { register : "UCA0CTL0" , regForceSet : false },
25 { register : "UCA0CTL1" , regForceSet : false },
26 { register : "UCA0BR0" , regForceSet : false },
27 { register : "UCA0BR1" , regForceSet : false },
28 { register : "UCA0MCTL" , regForceSet : false },
29 { register : "UCA0STAT" , regForceSet : false },
30 { register : "UCA0RXBUF" , regForceSet : false },
31 { register : "UCA0TXBUF" , regForceSet : false },
32 { register : "UCA0ABCTL" , regForceSet : false },
33 { register : "UCA0IRTCTL" , regForceSet : false },
34 { register : "UCA0IRRCTL" , regForceSet : false }
35 ];
36 }