1 /*!
2 * ======== ADC10 ========
3 * MSP430 10-bit Analog to Digital Converter
4 */
5 metaonly module ADC10 inherits IADC {
6
7 /*! ADC10 Start Conversion */
8 enum ADC10SC_t {
9 ADC10SC_OFF = 0x000, /*! No conversion. */
10 ADC10SC = 0x001 /*! Start ADC conversion manually. */
11 };
12
13 /*! ADC10 Enable Conversion */
14 enum ENC_t {
15 ENC_OFF = 0x000, /*! Disable ADC. */
16 ENC = 0x002 /*! Enable ADC. */
17 };
18
19 /*! ADC10 Interrupt Flag */
20 enum ADC10IFG_t {
21 ADC10IFG_OFF = 0x000, /*! Clear ADC interrupt flag. */
22 ADC10IFG = 0x004 /*! Set ADC interrupt flag. */
23 };
24
25 /*! ADC10 Interrupt Enable */
26 enum ADC10IE_t {
27 ADC10IE_OFF = 0x000, /*! Disable ADC interrupt. */
28 ADC10IE = 0x008 /*! Enable ADC interrupt. */
29 };
30
31 /*! ADC10 On/Enable */
32 enum ADC10ON_t {
33 ADC10ON_OFF = 0x000, /*! Switch Off ADC10. */
34 ADC10ON = 0x010 /*! Switch On ADC10. */
35 };
36
37 /*! ADC10 Reference on */
38 enum REFON_t {
39 REFON_OFF = 0x000, /*! Disable ADC reference generator. */
40 REFON = 0x020 /*! Enable ADC reference generator. */
41 };
42
43 /*! ADC10 Ref 0:1.5V / 1:2.5V */
44 enum REF2_5V_t {
45 REF2_5V_OFF = 0x000, /*! Set reference voltage generator = 1.5V. */
46 REF2_5V = 0x040 /*! Set reference voltage generator = 2.5V. */
47 };
48
49 /*! ADC10 Multiple SampleConversion */
50 enum MSC_t {
51 MSC_OFF = 0x000, /*! Disable multiple sample and conversion. */
52 MSC = 0x080 /*! Enable multiple sample and conversion. */
53 };
54
55 /*! ADC10 Reference Burst Mode */
56 enum REFBURST_t {
57 REFBURST_OFF = 0x000, /*! Reference buffer on continuously. */
58 REFBURST = 0x100 /*! Reference buffer on only during sample-and-conversion. */
59 };
60
61 /*! ADC10 Enable output of Ref. */
62 enum REFOUT_t {
63 REFOUT_OFF = 0x000, /*! Reference output off. */
64 REFOUT = 0x200 /*! Reference output on. */
65 };
66
67 /*! ADC10 Sampling Rate 0:200ksps / 1:50ksps */
68 enum ADC10SR_t {
69 ADC10SR_OFF = 0x000, /*! Reference buffer supports up to ~200 ksps. */
70 ADC10SR = 0x400 /*! Reference buffer supports up to ~50 ksps. */
71 };
72
73 /*! ADC10 Sample Hold Select 0 */
74 enum ADC10SHT_t {
75 ADC10SHT_0 = (0*0x800u), /*! 4 x ADC10CLKs. */
76 ADC10SHT_1 = (1*0x800u), /*! 8 x ADC10CLKs. */
77 ADC10SHT_2 = (2*0x800u), /*! 16 x ADC10CLKs. */
78 ADC10SHT_3 = 3*0x800u /*! 64 x ADC10CLKs. */
79 };
80
81 /*! ADC10 Reference Select 0 */
82 enum SREF_t {
83 SREF_0 = (0*0x2000u), /*! VR+ = VCC and VR- = VSS. */
84 SREF_1 = (1*0x2000u), /*! VR+ = VREF+ and VR- = VSS. */
85 SREF_2 = (2*0x2000u), /*! VR+ = VeREF+ and VR- = VSS. */
86 SREF_3 = (3*0x2000u), /*! VR+ = Buffered VeREF+ and VR- = VSS. */
87 SREF_4 = (4*0x2000u), /*! VR+ = VCC and VR- = VREF-/ VeREF-. */
88 SREF_5 = (5*0x2000u), /*! VR+ = VREF+ and VR- = VREF-/ VeREF-. */
89 SREF_6 = (6*0x2000u), /*! VR+ = VeREF+ and VR- = VREF-/ VeREF-. */
90 SREF_7 = 7*0x2000u /*! VR+ = Buffered VeREF+ and VR- = VREF-/ VeREF-. */
91 };
92
93 enum ADC10BUSY_t {
94 ADC10BUSY_OFF = 0x0000, /*! No operation is active. */
95 ADC10BUSY = 0x0001 /*! A sequence, sample, or conversion is active. */
96 };
97
98 /*! Types of conversion */
99 enum CONSEQ_t {
100 CONSEQ_0 = (0*2u), /*! Single channel single conversion. */
101 CONSEQ_1 = (1*2u), /*! Sequence of channels. */
102 CONSEQ_2 = (2*2u), /*! Repeat single channel. */
103 CONSEQ_3 = 3*2u /*! Repeat sequence of channels. */
104 };
105
106 /*! ADC10 Clock Source */
107 enum ADC10SSEL_t {
108 ADC10SSEL_0 = (0*8u), /*! ADC10OSC. */
109 ADC10SSEL_1 = (1*8u), /*! ACLK. */
110 ADC10SSEL_2 = (2*8u), /*! MCLK.*/
111 ADC10SSEL_3 = 3*8u /*! SMCLK. */
112 };
113
114 /*! ADC10 Clock Divider */
115 enum ADC10DIV_t {
116 ADC10DIV_0 = (0*0x20u), /*! Divide by 1. */
117 ADC10DIV_1 = (1*0x20u), /*! Divide by 2. */
118 ADC10DIV_2 = (2*0x20u), /*! Divide by 3. */
119 ADC10DIV_3 = (3*0x20u), /*! Divide by 4. */
120 ADC10DIV_4 = (4*0x20u), /*! Divide by 5. */
121 ADC10DIV_5 = (5*0x20u), /*! Divide by 6. */
122 ADC10DIV_6 = (6*0x20u), /*! Divide by 7. */
123 ADC10DIV_7 = 7*0x20u /*! Divide by 8. */
124 };
125
126 /*! ADC10 input signal inversion */
127 enum ISSH_t {
128 ISSH_OFF = 0x0000, /*! Input signal not inverted. */
129 ISSH = 0x0100 /*! Input signal inverted. */
130 };
131
132 /*! ADC10 output as 2's complement */
133 enum ADC10DF_t {
134 ADC10DF_OFF = 0x0000, /*! ADC10 Data Format as binary. */
135 ADC10DF = 0x0200 /*! ADC10 Data Format as 2's complement */
136 };
137
138 /*! ADC10 trigger */
139 enum SHS_t {
140 SHS_0 = (0*0x400u), /*! ADC10SC. */
141 SHS_1 = (1*0x400u), /*! Timer A3 OUT1. */
142 SHS_2 = (2*0x400u), /*! Timer A3 OUT0. */
143 SHS_3 = 3*0x400u /*! Timer A3 OUT2. */
144 };
145
146 /*! ADC10 Channel Selection */
147 enum INCH_t {
148 INCH_0 = (0*0x1000u), /*! ADC Channel 0. */
149 INCH_1 = (1*0x1000u), /*! ADC Channel 1. */
150 INCH_2 = (2*0x1000u), /*! ADC Channel 2. */
151 INCH_3 = (3*0x1000u), /*! ADC Channel 3. */
152 INCH_4 = (4*0x1000u), /*! ADC Channel 4. */
153 INCH_5 = (5*0x1000u), /*! ADC Channel 5. */
154 INCH_6 = (6*0x1000u), /*! ADC Channel 6. */
155 INCH_7 = (7*0x1000u), /*! ADC Channel 7. */
156 INCH_8 = (8*0x1000u), /*! ADC VeRef+. */
157 INCH_9 = (9*0x1000u), /*! ADC VeRef-. */
158 INCH_10 = (10*0x1000u), /*! Temperature Sensor. */
159 INCH_11 = (11*0x1000u), /*! ADC convert VCC. */
160 INCH_12 = (12*0x1000u), /*! ADC Channel 12. */
161 INCH_13 = (13*0x1000u), /*! ADC Channel 13. */
162 INCH_14 = (14*0x1000u), /*! ADC Channel 14. */
163 INCH_15 = 15*0x1000u /*! ADC Channel 15. */
164 };
165
166 /*!
167 * ======== ADC10CT_t ========
168 * Data transfer modes
169 *
170 * @see #ADC10DTC0
171 */
172 enum ADC10CT_t {
173 ADC10CT_OFF = 0x000, /*! Data is transferred is stopped after every conversion. */
174 ADC10CT = 0x004 /*! Data is transferred continuously after every conversion. */
175 }
176
177 /*!
178 * ======== ADC10TB_t ========
179 * Block data transfer modes
180 *
181 * @see #ADC10DTC0
182 */
183 enum ADC10TB_t {
184 ADC10TB_OFF = 0x000, /*! One-block transfer mode. */
185 ADC10TB = 0x008 /*! Two-block transfer mode. */
186 }
187
188
189 /*!
190 * ======== ADC10CTL0_t ========
191 * ADC10 Control Register 0
192 *
193 * @see #ADC10CTL0
194 */
195 struct ADC10CTL0_t {
196 ADC10SC_t ADC10SC; /*! Start conversion. Software-controlled sample-and-conversion start.
197 * ADC10SC and ENC may be set together with one instruction. ADC10SC is
198 * reset automatically.
199 * 0 No sample-and-conversion start
200 * 1 Start sample-and-conversion */
201 ENC_t ENC; /*! Enable conversion
202 * 0 ADC10 disabled
203 * 1 ADC10 enabled */
204 ADC10IFG_t ADC10IFG; /*! ADC10 interrupt flag. This bit is set if ADC10MEM is loaded with a conversion
205 * result. It is automatically reset when the interrupt request is accepted, or it may
206 * be reset by software. When using the DTC this flag is set when a block of
207 * transfers is completed.
208 * 0 No interrupt pending
209 * 1 Interrupt pending */
210 ADC10IE_t ADC10IE; /*! ADC10 interrupt enable
211 * 0 Interrupt disabled
212 * 1 Interrupt enabled */
213 ADC10ON_t ADC10ON; /*! ADC10 on
214 * 0 ADC10 off
215 * 1 ADC10 on */
216 REFON_t REFON; /*! Reference generator on
217 * 0 Reference off
218 * 1 Reference on */
219 REF2_5V_t REF2_5V; /*! Reference-generator voltage. REFON must also be set.
220 * 0 1.5 V
221 * 1 2.5 V */
222 MSC_t MSC; /*! Multiple sample and conversion. Valid only for sequence or repeated modes.
223 * 0 The sampling requires a rising edge of the SHI signal to trigger each
224 * sample-and-conversion.
225 * 1 The first rising edge of the SHI signal triggers the sampling timer, but
226 * further sample-and-conversions are performed automatically as soon
227 * as the prior conversion is completed */
228 REFBURST_t REFBURST; /*! Reference burst.
229 * 0 Reference buffer on continuously
230 * 1 Reference buffer on only during sample-and-conversion */
231 REFOUT_t REFOUT; /*! Reference output
232 * 0 Reference output off
233 * 1 Reference output on */
234 ADC10SR_t ADC10SR; /*! ADC10 sampling rate. This bit selects the reference buffer drive capability for
235 * the maximum sampling rate. Setting ADC10SR reduces the current
236 * consumption of the reference buffer.
237 * 0 Reference buffer supports up to ~200 ksps
238 * 1 Reference buffer supports up to ~50 ksps */
239 ADC10SHT_t ADC10SHT; /*! ADC10 sample-and-hold time
240 * 00 4 x ADC10CLKs
241 * 01 8 x ADC10CLKs
242 * 10 16 x ADC10CLKs
243 * 11 64 x ADC10CLKs */
244 SREF_t SREF; /*! Select reference
245 * 000 VR+ = VCC and VR- = VSS
246 * 001 VR+ = VREF+ and VR- = VSS
247 * 010 VR+ = VeREF+ and VR- = VSS
248 * 011 VR+ = Buffered VeREF+ and VR- = VSS
249 * 100 VR+ = VCC and VR- = VREF-/ VeREF-
250 * 101 VR+ = VREF+ and VR- = VREF-/ VeREF-
251 * 110 VR+ = VeREF+ and VR- = VREF-/ VeREF-
252 * 111 VR+ = Buffered VeREF+ and VR- = VREF-/ VeREF- */
253 }
254
255 /*!
256 * ======== ADC10CTL1_t ========
257 * ADC10 Control Register 1
258 *
259 * @see #ADC10CTL1
260 */
261 struct ADC10CTL1_t {
262 ADC10BUSY_t ADC10BUSY; /*! ADC10 busy. This bit indicates an active sample or conversion operation
263 * 0 No operation is active.
264 * 1 A sequence, sample, or conversion is active. */
265 CONSEQ_t CONSEQ; /*! Conversion sequence mode select
266 * 00 Single-channel-single-conversion
267 * 01 Sequence-of-channels
268 * 10 Repeat-single-channel
269 * 11 Repeat-sequence-of-channels */
270 ADC10SSEL_t ADC10SSEL; /*! ADC10 clock source select
271 * 00 ADC10OSC
272 * 01 ACLK
273 * 10 MCLK
274 * 11 SMCLK */
275 ADC10DIV_t ADC10DIV; /*! ADC10 clock divider
276 * 000 /1
277 * 001 /2
278 * 010 /3
279 * 011 /4
280 * 100 /5
281 * 101 /6
282 * 110 /7
283 * 111 /8 */
284 ISSH_t ISSH; /*! Invert signal sample-and-hold
285 * 0 The sample-input signal is not inverted.
286 * 1 The sample-input signal is inverted. */
287 ADC10DF_t ADC10DF; /*! ADC10 data format
288 * 0 Straight binary
289 * 1 2s complement */
290 SHS_t SHS; /*! Sample-and-hold source select
291 * 00 ADC10SC bit
292 * 01 Timer_A.OUT1
293 * 10 Timer_A.OUT0
294 * 11 Timer_A.OUT2 (Timer_A.OUT1 on MSP430x20x2 devices) */
295 INCH_t INCH; /*! Input channel select. These bits select the channel for a single-conversion or
296 * the highest channel for a sequence of conversions.
297 * 0000 A0
298 * 0001 A1
299 * 0010 A2
300 * 0011 A3
301 * 0100 A4
302 * 0101 A5
303 * 0110 A6
304 * 0111 A7
305 * 1000 VeREF+
306 * 1001 VREF-/VeREF-
307 * 1010 Temperature sensor
308 * 1011 (VCC ? VSS) / 2
309 * 1100 A12
310 * 1101 A13
311 * 1110 A14
312 * 1111 A15 */
313 }
314
315 /*!
316 * ======== ADC10DTC0_t ========
317 * Data Transfer Control Register 0
318 *
319 * @see #ADC10DTC0
320 */
321 struct ADC10DTC0_t {
322 ADC10TB_t ADC10TB; /*! ADC10 two-block mode
323 * 0 One-block transfer mode
324 * 1 Two-block transfer mode */
325 ADC10CT_t ADC10CT; /*! ADC10 continuous transfer
326 * 0 Data transfer stops when one block (one-block mode) or two blocks
327 * (two-block mode) have completed.
328 * 1 Data is transferred continuously. DTC operation is stopped only if
329 * ADC10CT cleared, or ADC10SA is written to. */
330 }
331
332 instance:
333 /*! Control Register 0 */
334 config ADC10CTL0_t ADC10CTL0 = {
335 ADC10SC : ADC10SC_OFF,
336 ENC : ENC_OFF,
337 ADC10IFG: ADC10IFG_OFF,
338 ADC10IE : ADC10IE_OFF,
339 ADC10ON : ADC10ON_OFF,
340 REFON : REFON_OFF,
341 REF2_5V : REF2_5V_OFF,
342 MSC : MSC_OFF,
343 REFBURST: REFBURST_OFF,
344 REFOUT : REFOUT_OFF,
345 ADC10SR : ADC10SR_OFF,
346 ADC10SHT: ADC10SHT_0,
347 SREF : SREF_0
348 };
349
350 /*! Control Register 1 */
351 config ADC10CTL1_t ADC10CTL1 = {
352 ADC10BUSY : ADC10BUSY_OFF,
353 CONSEQ : CONSEQ_0,
354 ADC10SSEL : ADC10SSEL_0,
355 ADC10DIV : ADC10DIV_0,
356 ISSH : ISSH_OFF,
357 ADC10DF : ADC10DF_OFF,
358 SHS : SHS_0,
359 INCH : INCH_0
360 };
361
362 /*!
363 * Analog (Input) Enable Control Register 0
364 *
365 * Bit n enables the corresponding pin for analog
366 * input. Bit 0 corresponds to A0, bit 1 corresponds to A1, ...
367 */
368 config Bits16 ADC10AE0 = 0;
369
370 /*!
371 * Analog (Input) Enable Control Register 1
372 *
373 * Bits 0, 1, 2, and 3 are reserved.
374 *
375 * Starting with bit 4, bit n enables pin n+8 for analog
376 * input: Bit 4 corresponds to A12, bit 5 corresponds to A13, ...
377 */
378 config Bits16 ADC10AE1 = 0;
379
380 /*! Data Transfer Control Register 0 */
381 config ADC10DTC0_t ADC10DTC0 = {
382 ADC10TB : ADC10TB_OFF,
383 ADC10CT : ADC10CT_OFF
384 };
385
386 /*!
387 * Data Transfer Control Register 1
388 *
389 * This register defines the number of transfers in each block: 0
390 * implies DTC is disabled, 1 through 0xff are valid transfer counts.
391 */
392 config Bits8 ADC10DTC1 = 0;
393
394 /*! Data Transfer Start Address */
395 config Bits16 ADC10SA = 0x200;
396
397 /*! Determine if each Register needs to be forced set or not */
398 readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
399 [
400 { register : "ADC10CTL0" , regForceSet : false },
401 { register : "ADC10CTL1" , regForceSet : false },
402 { register : "ADC10AE0" , regForceSet : false },
403 { register : "ADC10AE1" , regForceSet : false },
404 { register : "ADC10DTC0" , regForceSet : false },
405 { register : "ADC10DTC1" , regForceSet : false },
406 { register : "ADC10SA" , regForceSet : false }
407 ];
408 }