1 /*
2 * Copyright (c) 2010 by Texas Instruments and others.
3 * All rights reserved. This program and the accompanying materials
4 * are made available under the terms of the Eclipse Public License v1.0
5 * which accompanies this distribution, and is available at
6 * http://www.eclipse.org/legal/epl-v10.html
7 *
8 * Contributors:
9 * Texas Instruments - initial implementation
10 *
11 * */
12
13 /*
14 * ======== ITMS320TCI6608.xdc ========
15 *
16 */
17
18 package ti.catalog.c6000;
19
20 metaonly interface ITMS320TCI6608 inherits ti.catalog.ICpuDataSheet
21 {
22
23 config long cacheSizeL1[string] = [
24 ["0k", 0x0000],
25 ["4k", 0x1000],
26 ["8k", 0x2000],
27 ["16k", 0x4000],
28 ["32k", 0x8000],
29 ];
30
31 config long cacheSizeL2[string] = [
32 ["0k", 0x000000],
33 ["32k", 0x008000],
34 ["64k", 0x010000],
35 ["128k", 0x020000],
36 ["256k", 0x040000],
37 ["512k", 0x080000]
38 ];
39
40 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
41 ['l1PMode',{desc:"L1P Cache",
42 base: 0x00E00000,
43 map : [["0k",0x0000],
44 ["4k",0x1000],
45 ["8k",0x2000],
46 ["16k",0x4000],
47 ["32k",0x8000]],
48 defaultValue: "32k",
49 memorySection: "L1PSRAM"}],
50
51 ['l1DMode',{desc:"L1D Cache",
52 base: 0x00F00000,
53 map : [["0k",0x0000],
54 ["4k",0x1000],
55 ["8k",0x2000],
56 ["16k",0x4000],
57 ["32k",0x8000]],
58 defaultValue: "32k",
59 memorySection: "L1DSRAM"}],
60
61 ['l2Mode',{desc:"L2 Cache",
62 base: 0x00800000,
63 map : [["0k",0x0000],
64 ["32k",0x8000],
65 ["64k",0x10000],
66 ["128k", 0x020000],
67 ["256k", 0x040000],
68 ["512k", 0x080000]],
69 defaultValue: "0k",
70 memorySection: "L2SRAM"}],
71
72 ];
73
74 instance:
75
76 override config string cpuCore = "6600";
77 override config string isa = "66";
78 override config string cpuCoreRevision = "1.0";
79
80 override config int minProgUnitSize = 1;
81 override config int minDataUnitSize = 1;
82 override config int dataWordSize = 4;
83
84 /*!
85 * ======== memMap ========
86 * The default memory map for this device
87 */
88 config xdc.platform.IPlatform.Memory memMap[string] = [
89 ["L2SRAM", {
90 comment: "512KB L2 SRAM/CACHE",
91 name: "L2SRAM",
92 base: 0x00800000,
93 len: 0x00080000,
94 space: "code/data",
95 access: "RWX"
96 }],
97
98 ["L1PSRAM", {
99 comment: "32KB RAM/CACHE L1 program memory",
100 name: "L1PSRAM",
101 base: 0x00E00000,
102 len: 0x00008000,
103 space: "code",
104 access: "RWX"
105 }],
106
107 ["L1DSRAM", {
108 comment: "32KB RAM/CACHE L1 data memory",
109 name: "L1DSRAM",
110 base: 0x00F00000,
111 len: 0x00008000,
112 space: "data",
113 access: "RW"
114 }],
115
116 ["MSMCSRAM", {
117 comment: "4MB MSMC SRAM",
118 name: "MSMCSRAM",
119 base: 0x0C000000,
120 len: 0x00400000,
121 space: "code/data",
122 access: "RWX"
123 }],
124 ];
125 };
126 /*
127 * @(#) ti.catalog.c6000; 1, 0, 0, 0,291; 11-12-2010 14:43:11; /db/ztree/library/trees/platform/platform-l27x/src/
128 */
129