1 /*
2 * Copyright (c) 2010 by Texas Instruments and others.
3 * All rights reserved. This program and the accompanying materials
4 * are made available under the terms of the Eclipse Public License v1.0
5 * which accompanies this distribution, and is available at
6 * http://www.eclipse.org/legal/epl-v10.html
7 *
8 * Contributors:
9 * Texas Instruments - initial implementation
10 *
11 * */
12
13 /*
14 * ======== ITMS320CTCI6497.xdc ========
15 *
16 */
17
18 package ti.catalog.c6000;
19
20 metaonly interface ITMS320CTCI6497 inherits ti.catalog.ICpuDataSheet
21 {
22
23 config long cacheSizeL1[string] = [
24 ["0k", 0x0000],
25 ["4k", 0x1000],
26 ["8k", 0x2000],
27 ["16k", 0x4000],
28 ["32k", 0x8000],
29 ];
30
31 config long cacheSizeL2[string] = [
32 ["0k", 0x000000],
33 ["32k", 0x008000],
34 ["64k", 0x010000],
35 ["128k", 0x020000],
36 ["256k", 0x040000],
37 ["512k", 0x080000],
38 ["1024k", 0x100000]
39 ];
40
41 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
42 ['l1PMode',{desc:"L1P Cache",
43 base: 0x00E00000,
44 map : [["0k",0x0000],
45 ["4k",0x1000],
46 ["8k",0x2000],
47 ["16k",0x4000],
48 ["32k",0x8000]],
49 defaultValue: "32k",
50 memorySection: "L1PSRAM"}],
51
52 ['l1DMode',{desc:"L1D Cache",
53 base: 0x00F00000,
54 map : [["0k",0x0000],
55 ["4k",0x1000],
56 ["8k",0x2000],
57 ["16k",0x4000],
58 ["32k",0x8000]],
59 defaultValue: "32k",
60 memorySection: "L1DSRAM"}],
61
62 ['l2Mode',{desc:"L2 Cache",
63 base: 0x00800000,
64 map : [["0k",0x0000],
65 ["32k",0x8000],
66 ["64k",0x10000],
67 ["128k", 0x020000],
68 ["256k", 0x040000],
69 ["512k", 0x080000],
70 ["1024k", 0x100000]],
71 defaultValue: "0k",
72 memorySection: "L2SRAM"}],
73
74 ];
75
76 instance:
77
78 override config string cpuCore = "64x+";
79 override config string isa = "64P";
80 override config string cpuCoreRevision = "1.0";
81
82 override config int minProgUnitSize = 1;
83 override config int minDataUnitSize = 1;
84 override config int dataWordSize = 4;
85
86 /*!
87 * ======== memMap ========
88 * The default memory map for this device
89 */
90 config xdc.platform.IPlatform.Memory memMap[string] = [
91 ["L2SRAM", {
92 comment: "1MB L2 SRAM/CACHE",
93 name: "L2SRAM",
94 base: 0x00800000,
95 len: 0x00100000,
96 space: "code/data",
97 access: "RWX"
98 }],
99
100 ["L1PSRAM", {
101 comment: "32KB RAM/CACHE L1 program memory",
102 name: "L1PSRAM",
103 base: 0x00E00000,
104 len: 0x00008000,
105 space: "code",
106 access: "RWX"
107 }],
108
109 ["L1DSRAM", {
110 comment: "32KB RAM/CACHE L1 data memory",
111 name: "L1DSRAM",
112 base: 0x00F00000,
113 len: 0x00008000,
114 space: "data",
115 access: "RW"
116 }],
117
118 ["MSMCSRAM", {
119 comment: "2MB MSMC SRAM",
120 name: "MSMCSRAM",
121 base: 0x0C000000,
122 len: 0x00200000,
123 space: "code/data",
124 access: "RWX"
125 }],
126 ];
127 };
128 /*
129 * @(#) ti.catalog.c6000; 1, 0, 0, 0,291; 11-12-2010 14:43:11; /db/ztree/library/trees/platform/platform-l27x/src/
130 */
131