1 /*!
2 * ======== IUSCI ========
3 * Universal Serial Communication Interface
4 */
5 metaonly interface IUSCI inherits xdc.platform.IPeripheral {
6 7 8
9
10 /*! MSB first select. Controls the direction of the receive and transmit shift register. */
11 enum UCMSB_t {
12 UCMSB_OFF = 0x00, /*! LSB first */
13 UCMSB = 0x02 /*! MSB first */
14 };
15
16 /*! Character length. Selects 7-bit or 8-bit character length. */
17 enum UC7BIT_t {
18 UC7BIT_OFF = 0x00, /*! 8-bit */
19 UC7BIT = 0x02 /*! 7-bit */
20 };
21
22 /*! Synchronous mode enable */
23 enum UCSYNC_t {
24 UCSYNC_OFF = 0x00, /*! Asynchronous mode */
25 UCSYNC = 0x02 /*! Synchronous Mode */
26 };
27
28 /*! Receive erroneous-character interrupt-enable */
29 enum UCRXEIE_t {
30 UCRXEIE_OFF = 0x00, /*! Erroneous characters rejected and UCAxRXIFG is not set */
31 UCRXEIE = 0x02 /*! Erroneous characters received will set UCAxRXIFG */
32 };
33
34 /*! Receive break character interrupt-enable */
35 enum UCBRKIE_t {
36 UCBRKIE_OFF = 0x00, /*! Received break characters do not set UCAxRXIFG. */
37 UCBRKIE = 0x02 /*! Received break characters set UCAxRXIFG. */
38 };
39
40 /*! Dormant. Puts USCI into sleep mode. */
41 enum UCDORM_t {
42 UCDORM_OFF = 0x00, /*! Not dormant. All received characters will set UCAxRXIFG. */
43 UCDORM = 0x02 /*! Dormant. Only characters that are preceded by an idle-line or with
44 * address bit set will set UCAxRXIFG. In UART mode with automatic baud
45 * rate detection only the combination of a break and synch field will set
46 * UCAxRXIFG. */
47 };
48
49 /*! Transmit address. Next frame to be transmitted will be marked as address depending on the selected multiprocessor mode. */
50 enum UCTXADDR_t {
51 UCTXADDR_OFF = 0x00, /*! Next frame transmitted is data */
52 UCTXADDR = 0x02 /*! Next frame transmitted is an address */
53 };
54
55 /*! Transmit break. Transmits a break with the next write to the transmit buffer.
56 * In UART mode with automatic baud rate detection 055h must be written
57 * into UCAxTXBUF to generate the required break/synch fields. Otherwise
58 * 0h must be written into the transmit buffer. */
59 enum UCTXBRK_t {
60 UCTXBRK_OFF = 0x00, /*! Next frame transmitted is not a break */
61 UCTXBRK = 0x02 /*! Next frame transmitted is a break or a break/synch */
62 };
63
64 /*! Software reset enable */
65 enum UCSWRST_t {
66 UCSWRST_OFF = 0x00, /*! Disabled. USCI reset released for operation. */
67 UCSWRST = 0x02 /*! Enabled. USCI logic held in reset state. */
68 };
69
70 /*! Listen enable. The UCLISTEN bit selects loopback mode. */
71 enum UCLISTEN_t {
72 UCLISTEN_OFF = 0x00, /*! Disabled. */
73 UCLISTEN = 0x02 /*! Enabled. UCAxTXD is internally fed back to the receiver. */
74 };
75
76 /*! Framing error flag */
77 enum UCFE_t {
78 UCFE_OFF = 0x00, /*! 0 No error */
79 UCFE = 0x02 /*! Character received with low stop bit */
80 };
81
82 /*! Overrun error flag. */
83 enum UCOE_t {
84 UCOE_OFF = 0x00, /*! No error. */
85 UCOE = 0x02 /*! Overrun error occurred. */
86 };
87
88 /*! Parity error flag. When UCPEN = 0, UCPE is read as 0. */
89 enum UCPE_t {
90 UCPE_OFF = 0x00, /*! No error. */
91 UCPE = 0x02 /*! Character received with parity error. */
92 };
93
94 /*! Break detect flag */
95 enum UCBRK_t {
96 UCBRK_OFF = 0x00, /*! No break condition */
97 UCBRK = 0x02 /*! Break condition occurred */
98 };
99
100 /*! Bit 2 Receive error flag. This bit indicates a character was received with error(s).
101 * When UCRXERR = 1, on or more error flags (UCFE, UCPE, UCOE) is also
102 * set. UCRXERR is cleared when UCAxRXBUF is read. */
103 enum UCRXERR_t {
104 UCRXERR_OFF = 0x00, /*! No receive errors detected */
105 UCRXERR = 0x02 /*! Receive error detected */
106 };
107
108 /*! Address received in address-bit multiprocessor mode. */
109 enum UCADDR_t {
110 UCADDR_OFF = 0x00, /*! Received character is data */
111 UCADDR = 0x02 /*! Received character is an address */
112 };
113
114 /*! Idle line detected in idle-line multiprocessor mode. */
115 enum UCIDLE_t {
116 UCIDLE_OFF = 0x00, /*! No idle line detected */
117 UCIDLE = 0x02 /*! Idle line detected */
118 };
119
120 /*! USCI busy. This bit indicates if a transmit or receive operation is in progress. */
121 enum UCBUSY_t {
122 UCBUSY_OFF = 0x00, /*! USCI inactive */
123 UCBUSY = 0x01 /*! USCI transmitting or receiving */
124 };
125
126 /*! USCI mode. The UCMODEx bits select the synchronous mode when UCSYNC = 1. */
127 enum UCMODE_SYNC_t {
128 UCMODE_0 = 0x00, /*! 3-Pin SPI */
129 UCMODE_1 = 0x01, /*! 4-Pin SPI with UCxSTE active high: slave enabled when UCxSTE = 1 */
130 UCMODE_2 = 0x02, /*! 4-Pin SPI with UCxSTE active low: slave enabled when UCxSTE = 0 */
131 UCMODE_3 = 0x04 /*! I2C Mode */
132 };
133
134 /*!
135 * ======== ForceSetDefaultRegister_t ========
136 * Force Set Default Register
137 *
138 * Type to store if each register needs to be forced initialized
139 * even if the register is in default state.
140 *
141 * @see #ForceSetDefaultRegister_t
142 */
143 struct ForceSetDefaultRegister_t {
144 String register;
145 Bool regForceSet;
146 }
147
148 instance:
149 /*!
150 * Stores the UCLK external clock frequency in float
151 */
152 config float UCLKHz = 1000000;
153
154 bool setUCTXIE(bool set);
155
156 bool getUCTXIE();
157
158 bool setUCRXIE(bool set);
159
160 bool getUCRXIE();
161 }