1 /*
2 * Copyright (c) 2010 by Texas Instruments and others.
3 * All rights reserved. This program and the accompanying materials
4 * are made available under the terms of the Eclipse Public License v1.0
5 * which accompanies this distribution, and is available at
6 * http://www.eclipse.org/legal/epl-v10.html
7 *
8 * Contributors:
9 * Texas Instruments - initial implementation
10 *
11 * */
12
13 /*
14 * ======== TNETV107X.xdc ========
15 *
16 */
17 package ti.catalog.c6000;
18
19 /*!
20 * ======== TNETV107X ========
21 */
22 metaonly module TNETV107X inherits ti.catalog.ICpuDataSheet
23 {
24
25 config long cacheSizeL1[string] = [
26 ["0k", 0x0000],
27 ["4k", 0x1000],
28 ["8k", 0x2000],
29 ["16k", 0x4000],
30 ["32k", 0x8000],
31 ];
32
33 config long cacheSizeL2[string] = [
34 ["0k", 0x00000],
35 ["32k", 0x08000],
36 ["64k", 0x10000],
37 ["128k", 0x20000]
38 ];
39
40 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
41 ['l1PMode',
42 {desc: "L1P Cache",
43 map: [["0k", 0x0000],
44 ["4k", 0x1000],
45 ["8k", 0x2000],
46 ["16k", 0x4000],
47 ["32k", 0x8000]],
48 defaultValue: "0k",
49 memorySection: "L1PSRAM"}
50 ],
51
52 ['l1DMode',
53 {desc: "L1D Cache",
54 map: [["0k", 0x0000],
55 ["4k", 0x1000],
56 ["8k", 0x2000],
57 ["16k", 0x4000],
58 ["32k", 0x8000]],
59 defaultValue: "0k",
60 memorySection: "L1DSRAM"}
61 ],
62
63 ['l2Mode',
64 {desc: "L2 Cache",
65 map: [["0k", 0x0000],
66 ["32k", 0x8000],
67 ["64k", 0x10000],
68 ["128k", 0x20000]],
69 defaultValue: "0k",
70 memorySection: "L2RAM"}
71 ],
72
73 ];
74
75 instance:
76 override config int minProgUnitSize = 1;
77 override config int minDataUnitSize = 1;
78 override config int dataWordSize = 4;
79
80 override config string cpuCore = "64x+";
81 override config string isa = "64P";
82
83 config xdc.platform.IPlatform.Memory memMap[string] = [
84 ["L2RAM", {
85 comment: "Internal 128KB L2 memory",
86 name: "L2RAM",
87 base: 0x11800000,
88 len: 0x00020000,
89 space: "code/data",
90 access: "RWX"
91 }],
92
93 ["L1PSRAM", {
94 comment: "Internal 32KB L1 program memory",
95 name: "L1PSRAM",
96 base: 0x11E08000,
97 len: 0x00008000,
98 space: "code",
99 access: "RWX"
100 }],
101
102 ["L1DSRAM", {
103 comment: "Internal 80KB L1 data memory",
104 name: "L1DSRAM",
105 base: 0x11F04000,
106 len: 0x00014000,
107 space: "data",
108 access: "RW"
109 }],
110 ];
111 };
112 /*
113 * @(#) ti.catalog.c6000; 1, 0, 0, 0,276; 8-7-2010 18:18:13; /db/ztree/library/trees/platform/platform-l20x/src/
114 */
115