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13 14 15 16
17 package ti.catalog.c6000;
18
19 /*!
20 * ======== TMS320DA802 ========
21 * The DA802 device data sheet module.
22 */
23 metaonly module TMS320DA802 inherits ITMS320DA8xx
24 {
25 override config long cacheSizeL2[string] = [
26 ["0k", 0x00000],
27 ["32k", 0x08000],
28 ["64k", 0x10000],
29 ["128k", 0x20000]
30 ];
31
32 override readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
33 ['l1PMode',{desc:"L1P Cache",
34 map : [["0k",0x0000],
35 ["4k",0x1000],
36 ["8k",0x2000],
37 ["16k",0x4000],
38 ["32k",0x8000]],
39 defaultValue: "0k",
40 memorySection: "L1PSRAM"}],
41
42 ['l1DMode',{desc:"L1D Cache",
43 map : [["0k",0x0000],
44 ["4k",0x1000],
45 ["8k",0x2000],
46 ["16k",0x4000],
47 ["32k",0x8000]],
48 defaultValue: "0k",
49 memorySection: "L1DSRAM"}],
50
51 ['l2Mode',{desc:"L2 Cache",
52 map : [["0k",0x0000],
53 ["32k",0x8000],
54 ["64k",0x10000],
55 ["128k",0x20000]],
56 defaultValue: "0k",
57 memorySection: "IRAM"}],
58
59 ];
60
61
62 instance:
63
64 /*!
65 * ======== memMap ========
66 * The default memory map for this device
67 */
68 override config xdc.platform.IPlatform.Memory memMap[string] = [
69 ["IROM", {
70 comment: "Internal 1MB L2 ROM",
71 name: "IROM",
72 base: 0x11700000,
73 len: 0x00100000,
74 space: "code/data",
75 access: "RX"
76 }],
77
78 ["IRAM", {
79 comment: "Internal 128KB L2 memory",
80 name: "IRAM",
81 base: 0x11800000,
82 len: 0x00020000,
83 space: "code/data",
84 access: "RWX"
85 }],
86
87 ["L1PSRAM", {
88 comment: "Internal 32KB L1 program memory",
89 name: "L1PSRAM",
90 base: 0x11E00000,
91 len: 0x00008000,
92 space: "code",
93 access: "RWX"
94 }],
95
96 ["L1DSRAM", {
97 comment: "Internal 32KB L1 data memory",
98 name: "L1DSRAM",
99 base: 0x11F00000,
100 len: 0x00008000,
101 space: "data",
102 access: "RW"
103 }],
104 ];
105 };
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109