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17
18 package ti.catalog.c6000;
19
20 /*!
21 * ======== TMS320CDM6431 ========
22 * The DM6431 device data sheet module.
23 *
24 * This module implements the xdc.platform.ICpuDataSheet interface and is
25 * used by platforms to obtain "data sheet" information about this device.
26 */
27 metaonly module TMS320CDM6431 inherits ti.catalog.ICpuDataSheet
28 {
29 config long cacheSizeL1[string] = [
30 ["0k", 0x0000],
31 ["4k", 0x1000],
32 ["8k", 0x2000],
33 ["16k", 0x4000],
34 ["32k", 0x8000]
35 ];
36
37 config long cacheSizeL2[string] = [
38 ["0k", 0x00000],
39 ["32k", 0x08000],
40 ["64k", 0x10000]
41 ];
42
43 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
44 ['l1PMode',{desc:"L1P Cache",
45 map : [["0k",0x0000],
46 ["4k",0x1000],
47 ["8k",0x2000],
48 ["16k",0x4000],
49 ["32k",0x8000]],
50 defaultValue: "0k",
51 memorySection: "L1PSRAM"}],
52
53 ['l1DMode',{desc:"L1D Cache",
54 map : [["0k",0x0000],
55 ["4k",0x1000],
56 ["8k",0x2000],
57 ["16k",0x4000],
58 ["32k",0x8000]],
59 defaultValue: "0k",
60 memorySection: "L1DSRAM"}],
61
62 ['l2Mode',{desc:"L2 Cache",
63 map : [["0k",0x0000],
64 ["32k",0x8000],
65 ["64k",0x10000]],
66 defaultValue: "0k",
67 memorySection: "IRAM"}],
68 ];
69
70 instance:
71
72 override config string cpuCore = "64x+";
73 override config string isa = "64P";
74 override config string cpuCoreRevision = "1.0";
75
76 override config int minProgUnitSize = 1;
77 override config int minDataUnitSize = 1;
78 override config int dataWordSize = 4;
79
80 /*!
81 * ======== memMap ========
82 * The default memory map for this device
83 */
84 config xdc.platform.IPlatform.Memory memMap[string] = [
85 ["IRAM", {
86 comment: "Internal 64KB L2 RAM/CACHE in UMAP0 memory",
87 name: "IRAM",
88 base: 0x10810000,
89 len: 0x00010000,
90 space: "code/data",
91 access: "RWX"
92 }],
93
94 ["L1PSRAM", {
95 comment: "Internal 32KB RAM/CACHE L1 program memory",
96 name: "L1PSRAM",
97 base: 0x10E08000,
98 len: 0x00008000,
99 space: "code",
100 access: "RWX"
101 }],
102
103 ["L1DSRAM", {
104 comment: "Internal 32KB RAM/CACHE L1 data memory",
105 name: "L1DSRAM",
106 base: 0x10F10000,
107 len: 0x00008000,
108 space: "data",
109 access: "RW"
110 }],
111 ];
112 };
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