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13 14 15 16
17
18 package ti.catalog.c6000;
19
20 metaonly interface ITMS320TCI6616 inherits ti.catalog.ICpuDataSheet
21 {
22
23 config long cacheSizeL1[string] = [
24 ["0k", 0x0000],
25 ["4k", 0x1000],
26 ["8k", 0x2000],
27 ["16k", 0x4000],
28 ["32k", 0x8000],
29 ];
30
31 config long cacheSizeL2[string] = [
32 ["0k", 0x000000],
33 ["32k", 0x008000],
34 ["64k", 0x010000],
35 ["128k", 0x020000],
36 ["256k", 0x040000],
37 ["512k", 0x080000],
38 ["1024k", 0x100000]
39 ];
40
41 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
42 ['l1PMode',{desc:"L1P Cache",
43 map : [["0k",0x0000],
44 ["4k",0x1000],
45 ["8k",0x2000],
46 ["16k",0x4000],
47 ["32k",0x8000]],
48 defaultValue: "0k",
49 memorySection: "L1PSRAM"}],
50
51 ['l1DMode',{desc:"L1D Cache",
52 map : [["0k",0x0000],
53 ["4k",0x1000],
54 ["8k",0x2000],
55 ["16k",0x4000],
56 ["32k",0x8000]],
57 defaultValue: "0k",
58 memorySection: "L1DSRAM"}],
59
60 ['l2Mode',{desc:"L2 Cache",
61 map : [["0k",0x0000],
62 ["32k",0x8000],
63 ["64k",0x10000],
64 ["128k", 0x020000],
65 ["256k", 0x040000],
66 ["512k", 0x080000],
67 ["1024k", 0x100000]],
68 defaultValue: "0k",
69 memorySection: "L2SRAM"}],
70
71 ];
72
73 instance:
74
75 override config string cpuCore = "6600";
76 override config string isa = "66";
77 override config string cpuCoreRevision = "1.0";
78
79 override config int minProgUnitSize = 1;
80 override config int minDataUnitSize = 1;
81 override config int dataWordSize = 4;
82
83 /*!
84 * ======== memMap ========
85 * The default memory map for this device
86 */
87 config xdc.platform.IPlatform.Memory memMap[string] = [
88 ["L2SRAM", {
89 comment: "1MB L2 SRAM/CACHE",
90 name: "L2SRAM",
91 base: 0x00800000,
92 len: 0x00100000,
93 space: "code/data",
94 access: "RWX"
95 }],
96
97 ["L1PSRAM", {
98 comment: "32KB RAM/CACHE L1 program memory",
99 name: "L1PSRAM",
100 base: 0x00E00000,
101 len: 0x00008000,
102 space: "code",
103 access: "RWX"
104 }],
105
106 ["L1DSRAM", {
107 comment: "32KB RAM/CACHE L1 data memory",
108 name: "L1DSRAM",
109 base: 0x00F00000,
110 len: 0x00008000,
111 space: "data",
112 access: "RW"
113 }],
114
115 ["MSMCSRAM", {
116 comment: "2MB MSMC SRAM",
117 name: "MSMCSRAM",
118 base: 0x0C000000,
119 len: 0x00200000,
120 space: "code/data",
121 access: "RWX"
122 }],
123 ];
124 };
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