1 /*
2 * Copyright (c) 2010 by Texas Instruments and others.
3 * All rights reserved. This program and the accompanying materials
4 * are made available under the terms of the Eclipse Public License v1.0
5 * which accompanies this distribution, and is available at
6 * http://www.eclipse.org/legal/epl-v10.html
7 *
8 * Contributors:
9 * Texas Instruments - initial implementation
10 *
11 * */
12
13 /*
14 * ======== ITMS320TCI6608.xdc ========
15 *
16 */
17
18 package ti.catalog.c6000;
19
20 metaonly interface ITMS320TCI6608 inherits ti.catalog.ICpuDataSheet
21 {
22
23 config long cacheSizeL1[string] = [
24 ["0k", 0x0000],
25 ["4k", 0x1000],
26 ["8k", 0x2000],
27 ["16k", 0x4000],
28 ["32k", 0x8000],
29 ];
30
31 config long cacheSizeL2[string] = [
32 ["0k", 0x000000],
33 ["32k", 0x008000],
34 ["64k", 0x010000],
35 ["128k", 0x020000],
36 ["256k", 0x040000],
37 ["512k", 0x080000]
38 ];
39
40 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
41 ['l1PMode',{desc:"L1P Cache",
42 map : [["0k",0x0000],
43 ["4k",0x1000],
44 ["8k",0x2000],
45 ["16k",0x4000],
46 ["32k",0x8000]],
47 defaultValue: "0k",
48 memorySection: "L1PSRAM"}],
49
50 ['l1DMode',{desc:"L1D Cache",
51 map : [["0k",0x0000],
52 ["4k",0x1000],
53 ["8k",0x2000],
54 ["16k",0x4000],
55 ["32k",0x8000]],
56 defaultValue: "0k",
57 memorySection: "L1DSRAM"}],
58
59 ['l2Mode',{desc:"L2 Cache",
60 map : [["0k",0x0000],
61 ["32k",0x8000],
62 ["64k",0x10000],
63 ["128k", 0x020000],
64 ["256k", 0x040000],
65 ["512k", 0x080000]],
66 defaultValue: "0k",
67 memorySection: "L2SRAM"}],
68
69 ];
70
71 instance:
72
73 override config string cpuCore = "6600";
74 override config string isa = "66";
75 override config string cpuCoreRevision = "1.0";
76
77 override config int minProgUnitSize = 1;
78 override config int minDataUnitSize = 1;
79 override config int dataWordSize = 4;
80
81 /*!
82 * ======== memMap ========
83 * The default memory map for this device
84 */
85 config xdc.platform.IPlatform.Memory memMap[string] = [
86 ["L2SRAM", {
87 comment: "512KB L2 SRAM/CACHE",
88 name: "L2SRAM",
89 base: 0x00800000,
90 len: 0x00080000,
91 space: "code/data",
92 access: "RWX"
93 }],
94
95 ["L1PSRAM", {
96 comment: "32KB RAM/CACHE L1 program memory",
97 name: "L1PSRAM",
98 base: 0x00E00000,
99 len: 0x00008000,
100 space: "code",
101 access: "RWX"
102 }],
103
104 ["L1DSRAM", {
105 comment: "32KB RAM/CACHE L1 data memory",
106 name: "L1DSRAM",
107 base: 0x00F00000,
108 len: 0x00008000,
109 space: "data",
110 access: "RW"
111 }],
112
113 ["MSMCSRAM", {
114 comment: "4MB MSMC SRAM",
115 name: "MSMCSRAM",
116 base: 0x0C000000,
117 len: 0x00400000,
118 space: "code/data",
119 access: "RWX"
120 }],
121 ];
122 };
123 /*
124 * @(#) ti.catalog.c6000; 1, 0, 0, 0,276; 8-7-2010 18:18:09; /db/ztree/library/trees/platform/platform-l20x/src/
125 */
126