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13 14 15 16
17 package ti.catalog.c6000;
18
19 /*!
20 * ======== ITMS320DA8xx ========
21 * An interface implemented by TMS320DA8xx devices.
22 *
23 */
24 metaonly interface ITMS320DA8xx inherits ti.catalog.ICpuDataSheet
25 {
26
27 config long cacheSizeL1[string] = [
28 ["0k", 0x0000],
29 ["4k", 0x1000],
30 ["8k", 0x2000],
31 ["16k", 0x4000],
32 ["32k", 0x8000],
33 ];
34
35 config long cacheSizeL2[string] = [
36 ["0k", 0x00000],
37 ["32k", 0x08000],
38 ["64k", 0x10000],
39 ["128k",0x20000],
40 ["256k",0x40000],
41 ];
42
43 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
44 ['l1PMode',{desc:"L1P Cache",
45 map : [["0k",0x0000],
46 ["4k",0x1000],
47 ["8k",0x2000],
48 ["16k",0x4000],
49 ["32k",0x8000]],
50 defaultValue: "0k",
51 memorySection: "L1PSRAM"}],
52
53 ['l1DMode',{desc:"L1D Cache",
54 map : [["0k",0x0000],
55 ["4k",0x1000],
56 ["8k",0x2000],
57 ["16k",0x4000],
58 ["32k",0x8000]],
59 defaultValue: "0k",
60 memorySection: "L1DSRAM"}],
61
62 ['l2Mode',{desc:"L2 Cache",
63 map : [["0k",0x0000],
64 ["32k",0x8000],
65 ["64k",0x10000],
66 ["128k",0x20000],
67 ["256k",0x40000]],
68 defaultValue: "0k",
69 memorySection: "IRAM"}],
70
71 ];
72
73 instance:
74 override config int minProgUnitSize = 1;
75 override config int minDataUnitSize = 1;
76 override config int dataWordSize = 4;
77
78 override config string cpuCore = "C674";
79 override config string isa = "674";
80 override config string cpuCoreRevision = "1.0";
81
82 config xdc.platform.IPlatform.Memory memMap[string] = [
83 ["IROM", {
84 comment: "Internal 1MB L2 ROM",
85 name: "IROM",
86 base: 0x11700000,
87 len: 0x00100000,
88 space: "code/data",
89 access: "RX"
90 }],
91
92 ["IRAM", {
93 comment: "Internal 256KB L2 memory",
94 name: "IRAM",
95 base: 0x11800000,
96 len: 0x00040000,
97 space: "code/data",
98 access: "RWX"
99 }],
100
101 ["L1PSRAM", {
102 comment: "Internal 32KB L1 program memory",
103 name: "L1PSRAM",
104 base: 0x11E00000,
105 len: 0x00008000,
106 space: "code",
107 access: "RWX"
108 }],
109
110 ["L1DSRAM", {
111 comment: "Internal 32KB L1 data memory",
112 name: "L1DSRAM",
113 base: 0x11F00000,
114 len: 0x00008000,
115 space: "data",
116 access: "RW"
117 }],
118
119 ["L3_CBA_RAM", {
120 comment: "128KB ARM/DSP local shared RAM",
121 name: "L3_CBA_RAM",
122 base: 0x80000000,
123 len: 0x00020000,
124 space: "code/data",
125 access: "RWX"
126 }],
127 ];
128 };
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132