1 /*
2 * Copyright (c) 2010 by Texas Instruments and others.
3 * All rights reserved. This program and the accompanying materials
4 * are made available under the terms of the Eclipse Public License v1.0
5 * which accompanies this distribution, and is available at
6 * http://www.eclipse.org/legal/epl-v10.html
7 *
8 * Contributors:
9 * Texas Instruments - initial implementation
10 *
11 * */
12
13 /*
14 * ======== ITMS320CTCI648x.xdc ========
15 *
16 */
17
18 /*!
19 * ======== ITMS320CTCI648x ========
20 * An interface implemented by TCI6487 and TCI6488 devices
21 *
22 * This interface is defined to factor common data about TCI6487 and TCI6488
23 * devices into a single place; they are all the same from the configuration
24 * point of view.
25 */
26 metaonly interface ITMS320CTCI648x inherits ti.catalog.ICpuDataSheet
27 {
28
29 config long cacheSizeL1[string] = [
30 ["0k", 0x0000],
31 ["4k", 0x1000],
32 ["8k", 0x2000],
33 ["16k", 0x4000],
34 ["32k", 0x8000],
35 ];
36
37 config long cacheSizeL2[string] = [
38 ["0k", 0x00000],
39 ["32k", 0x08000],
40 ["64k", 0x10000],
41 ["128k", 0x20000],
42 ["256k", 0x40000]
43 ];
44
45 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
46 ['l1PMode',{desc:"L1P Cache",
47 map : [["0k",0x0000],
48 ["4k",0x1000],
49 ["8k",0x2000],
50 ["16k",0x4000],
51 ["32k",0x8000]],
52 defaultValue: "0k",
53 memorySection: "L1PSRAM"}],
54
55 ['l1DMode',{desc:"L1D Cache",
56 map : [["0k",0x0000],
57 ["4k",0x1000],
58 ["8k",0x2000],
59 ["16k",0x4000],
60 ["32k",0x8000]],
61 defaultValue: "0k",
62 memorySection: "L1DSRAM"}],
63
64 ['l2Mode',{desc:"L2 Cache",
65 map : [["0k",0x0000],
66 ["32k",0x8000],
67 ["64k",0x10000],
68 ["128k",0x20000],
69 ["256k",0x40000]],
70 defaultValue: "0k",
71 memorySection: "L2RAM"}]
72
73 ];
74
75 config xdc.platform.IPlatform.Memory memBlock[string] = [
76 ["ASYMGEM0L2RAM", {
77 comment: "1536K L2 RAM/CACHE memory",
78 name: "L2RAM",
79 base: 0x00800000,
80 len: 0x00180000,
81 space: "code/data",
82 access: "RWX"
83 }],
84
85 ["ASYMGEM1L2RAM", {
86 comment: "1024K L2 RAM/CACHE memory",
87 name: "L2RAM",
88 base: 0x00800000,
89 len: 0x00100000,
90 space: "code/data",
91 access: "RWX"
92 }],
93
94 ["ASYMGEM2L2RAM", {
95 comment: "512K L2 RAM/CACHE memory",
96 name: "L2RAM",
97 base: 0x00800000,
98 len: 0x00080000,
99 space: "code/data",
100 access: "RWX"
101 }],
102
103 ["SYMGEML2RAM", {
104 comment: "1024K L2 RAM/CACHE memory",
105 name: "L2RAM",
106 base: 0x00800000,
107 len: 0x00100000,
108 space: "code/data",
109 access: "RWX"
110 }],
111
112 ];
113
114 instance:
115
116 override config string cpuCore = "64x+";
117 override config string isa = "64P";
118 override config string cpuCoreRevision = "1.0";
119
120 override config int minProgUnitSize = 1;
121 override config int minDataUnitSize = 1;
122 override config int dataWordSize = 4;
123
124 /*!
125 * ======== memMap ========
126 * The default memory map for this device
127 */
128 config xdc.platform.IPlatform.Memory memMap[string] = [
129
130 ["L1PSRAM", {
131 comment: "Internal 32KB RAM/CACHE L1 program memory",
132 name: "L1PSRAM",
133 base: 0xE00000,
134 len: 0x008000,
135 space: "code",
136 access: "RWX"
137 }],
138
139 ["L1DSRAM", {
140 comment: "Internal 32KB RAM/CACHE L1 data memory",
141 name: "L1DSRAM",
142 base: 0xF00000,
143 len: 0x008000,
144 space: "data",
145 access: "RW"
146 }],
147 ];
148
149 };
150 /*
151 * @(#) ti.catalog.c6000; 1, 0, 0, 0,276; 8-7-2010 18:18:09; /db/ztree/library/trees/platform/platform-l20x/src/
152 */
153