1 /*
2 * Copyright (c) 2010 by Texas Instruments and others.
3 * All rights reserved. This program and the accompanying materials
4 * are made available under the terms of the Eclipse Public License v1.0
5 * which accompanies this distribution, and is available at
6 * http://www.eclipse.org/legal/epl-v10.html
7 *
8 * Contributors:
9 * Texas Instruments - initial implementation
10 *
11 * */
12
13 /*
14 * ======== ITMS320CDRA45x.xdc ========
15 *
16 */
17
18 /*!
19 * ======== ITMS320CDRA45x ========
20 * An interface implemented by all DRA45x devices
21 *
22 * This interface is defined to factor common data about all DRA45x devices
23 * into a single place; they are all the same from the configuration point of
24 * view.
25 */
26 metaonly interface ITMS320CDRA45x inherits ti.catalog.ICpuDataSheet
27 {
28 config long cacheSizeL1[string] = [
29 ["0k", 0x0000],
30 ["4k", 0x1000],
31 ["8k", 0x2000],
32 ["16k", 0x4000],
33 ["32k", 0x8000],
34 ];
35
36 config long cacheSizeL2[string] = [
37 ["0k", 0x00000],
38 ["32k", 0x08000],
39 ["64k", 0x10000],
40 ["128k", 0x20000]
41 ];
42
43 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
44 ['l1PMode',{desc:"L1P Cache",
45 map : [["0k",0x0000],
46 ["4k",0x1000],
47 ["8k",0x2000],
48 ["16k",0x4000],
49 ["32k",0x8000]],
50 defaultValue: "0k",
51 memorySection: "L1PSRAM"}],
52
53 ['l1DMode',{desc:"L1D Cache",
54 map : [["0k",0x0000],
55 ["4k",0x1000],
56 ["8k",0x2000],
57 ["16k",0x4000],
58 ["32k",0x8000]],
59 defaultValue: "0k",
60 memorySection: "L1DSRAM"}],
61
62 ['l2Mode',{desc:"L2 Cache",
63 map : [["0k",0x0000],
64 ["32k",0x8000],
65 ["64k",0x10000],
66 ["128k",0x20000]],
67 defaultValue: "0k",
68 memorySection: "IRAM"}],
69
70 ];
71
72 instance:
73
74 override config string cpuCore = "64x+";
75 override config string isa = "64P";
76 override config string cpuCoreRevision = "1.0";
77
78 override config int minProgUnitSize = 1;
79 override config int minDataUnitSize = 1;
80 override config int dataWordSize = 4;
81
82 /*!
83 * ======== memMap ========
84 * The default memory map for this device
85 */
86 config xdc.platform.IPlatform.Memory memMap[string] = [
87 ["IRAM", {
88 comment: "Internal 128KB UMAP0 memory",
89 name: "IRAM",
90 base: 0x11800000,
91 len: 0x00020000,
92 space: "code/data",
93 access: "RWX"
94 }],
95
96 ["L1PSRAM", {
97 comment: "Internal 32KB RAM/CACHE L1 program memory",
98 name: "L1PSRAM",
99 base: 0x11E08000,
100 len: 0x00008000,
101 space: "code",
102 access: "RWX"
103 }],
104
105 ["L1DSRAM", {
106 comment: "Internal 80KB RAM/CACHE L1 data memory",
107 name: "L1DSRAM",
108 base: 0x11F04000,
109 len: 0x00014000,
110 space: "data",
111 access: "RW"
112 }],
113
114 ["ARM_RAM", {
115 comment: "Internal ARM RAM memory",
116 name: "ARM_RAM",
117 base: 0x10008000,
118 len: 0x00004000,
119 space: "data",
120 access: "RW"
121 }],
122 ];
123 };
124 /*
125 * @(#) ti.catalog.c6000; 1, 0, 0, 0,276; 8-7-2010 18:18:09; /db/ztree/library/trees/platform/platform-l20x/src/
126 */
127