1    /*
     2     *  Copyright (c) 2010 by Texas Instruments and others.
     3     *  All rights reserved. This program and the accompanying materials
     4     *  are made available under the terms of the Eclipse Public License v1.0
     5     *  which accompanies this distribution, and is available at
     6     *  http://www.eclipse.org/legal/epl-v10.html
     7     *
     8     *  Contributors:
     9     *      Texas Instruments - initial implementation
    10     *
    11     * */
    12    
    13    /*
    14     *  ======== ITMS320CDRA44x.xdc ========
    15     *
    16     */
    17    
    18    /*!
    19     *  ======== ITMS320CDRA44x ========
    20     *  An interface implemented by all DRA44x devices
    21     *
    22     *  This interface is defined to factor common data about all DRA44x devices
    23     *  into a single place; they are all the same from the configuration point of
    24     *  view.
    25     */
    26    metaonly interface ITMS320CDRA44x inherits ti.catalog.ICpuDataSheet
    27    {
    28        config long cacheSizeL1[string] = [
    29            ["0k",  0x0000],
    30            ["4k",  0x1000],
    31            ["8k",  0x2000],
    32            ["16k", 0x4000],
    33            ["32k", 0x8000],
    34        ];
    35    
    36        config long cacheSizeL2[string] = [
    37            ["0k",  0x00000],
    38            ["32k", 0x08000],
    39            ["64k", 0x10000]
    40        ];
    41    
    42        readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] =  [
    43             ['l1PMode',{desc:"L1P Cache",
    44                         map : [["0k",0x0000],
    45                                ["4k",0x1000],
    46                                ["8k",0x2000],
    47                                ["16k",0x4000],
    48                                ["32k",0x8000]],
    49                         defaultValue: "0k",
    50                         memorySection: "L1PSRAM"}],
    51         
    52                     ['l1DMode',{desc:"L1D Cache",
    53                         map : [["0k",0x0000],
    54                                ["4k",0x1000],
    55                                ["8k",0x2000],
    56                                ["16k",0x4000],
    57                                ["32k",0x8000]],
    58                         defaultValue: "0k",
    59                         memorySection: "L1DSRAM"}],
    60                     
    61             ['l2Mode',{desc:"L2 Cache",
    62                         map : [["0k",0x0000],
    63                                ["32k",0x8000],
    64                                ["64k",0x10000]],
    65                         defaultValue: "0k",
    66                         memorySection: "IRAM"}]
    67    
    68        ];
    69    
    70    instance:
    71        
    72        override config string   cpuCore        = "64x+";
    73        override config string   isa            = "64P";
    74        override config string   cpuCoreRevision = "1.0";
    75    
    76        override config int     minProgUnitSize = 1;
    77        override config int     minDataUnitSize = 1;    
    78        override config int     dataWordSize    = 4;
    79    
    80        /*!
    81         *  ======== memMap ========
    82         *  The default memory map for this device
    83         */
    84        config xdc.platform.IPlatform.Memory memMap[string]  = [
    85            ["IRAM", {
    86                comment:    "Internal 64KB UMAP0 memory",
    87                name:       "IRAM",
    88                base:       0x11800000,
    89                len:        0x00010000,
    90                space:      "code/data",
    91                access:     "RWX"
    92            }],
    93    
    94            ["L1PSRAM", {
    95                comment:    "Internal 32KB RAM/CACHE L1 program memory",
    96                name:       "L1PSRAM",
    97                base:       0x11E08000,
    98                len:        0x00008000,
    99                space:      "code",
   100                access:     "RWX"
   101            }],
   102    
   103            ["L1DSRAM", {
   104                comment:    "Internal 80KB RAM/CACHE L1 data memory",
   105                name:       "L1DSRAM",
   106                base:       0x11F04000,
   107                len:        0x00014000,
   108                space:      "data",
   109                access:     "RW"
   110            }],
   111    
   112            ["ARM_RAM", {
   113                comment:    "Internal ARM RAM memory",
   114                name:       "ARM_RAM",
   115                base:       0x10008000,
   116                len:        0x00004000,
   117                space:      "data",
   118                access:     "RW"
   119            }],
   120        ];
   121    };
   122    /*
   123     *  @(#) ti.catalog.c6000; 1, 0, 0, 0,276; 8-7-2010 18:18:09; /db/ztree/library/trees/platform/platform-l20x/src/
   124     */
   125