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13 14 15 16
17 package ti.catalog.c6000;
18
19 /*!
20 * ======== ITMS320CDM6467 ========
21 * An interface implemented by all DaVinci-HD devices
22 *
23 * This interface is defined to factor common data about all DaVinci-HD devices
24 * into a single place; they are all the same from the configuration point of
25 * view.
26 */
27 metaonly interface ITMS320CDM6467 inherits ti.catalog.ICpuDataSheet
28 {
29 config long cacheSizeL1[string] = [
30 ["0k", 0x0000],
31 ["4k", 0x1000],
32 ["8k", 0x2000],
33 ["16k", 0x4000],
34 ["32k", 0x8000],
35 ];
36
37 config long cacheSizeL2[string] = [
38 ["0k", 0x00000],
39 ["32k", 0x08000],
40 ["64k", 0x10000],
41 ["128k", 0x20000],
42 ];
43
44 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
45 ['l1PMode',{desc:"L1P Cache",
46 map : [["0k",0x0000],
47 ["4k",0x1000],
48 ["8k",0x2000],
49 ["16k",0x4000],
50 ["32k",0x8000]],
51 defaultValue: "0k",
52 memorySection: "L1PSRAM"}],
53
54 ['l1DMode',{desc:"L1D Cache",
55 map : [["0k",0x0000],
56 ["4k",0x1000],
57 ["8k",0x2000],
58 ["16k",0x4000],
59 ["32k",0x8000]],
60 defaultValue: "0k",
61 memorySection: "L1DSRAM"}],
62
63 ['l2Mode',{desc:"L2 Cache",
64 map : [["0k",0x0000],
65 ["32k",0x8000],
66 ["64k",0x10000],
67 ["128k",0x20000]],
68 defaultValue: "0k",
69 memorySection: "IRAM"}]
70
71 ];
72
73 instance:
74
75 override config string cpuCore = "64x+";
76 override config string isa = "64P";
77 override config string cpuCoreRevision = "1.0";
78
79 override config int minProgUnitSize = 1;
80 override config int minDataUnitSize = 1;
81 override config int dataWordSize = 4;
82
83 /*!
84 * ======== memMap ========
85 * The default memory map for this device
86 */
87 config xdc.platform.IPlatform.Memory memMap[string] = [
88 ["ARM_RAM", {
89 comment: "Internal ARM RAM memory",
90 name: "ARM_RAM",
91 base: 0x10010000,
92 len: 0x00008000,
93 space: "data",
94 access: "RW"
95 }],
96
97 ["IRAM", {
98 comment: "Internal 128KB UMAP0 memory",
99 name: "IRAM",
100 base: 0x11818000,
101 len: 0x00020000,
102 space: "code/data",
103 access: "RWX"
104 }],
105
106 ["L1PSRAM", {
107 comment: "Internal 32KB RAM/CACHE L1 program memory",
108 name: "L1PSRAM",
109 base: 0x11E00000,
110 len: 0x00008000,
111 space: "code",
112 access: "RWX"
113 }],
114
115 ["L1DSRAM", {
116 comment: "Internal 32KB RAM/CACHE L1 data memory",
117 name: "L1DSRAM",
118 base: 0x11F00000,
119 len: 0x00008000,
120 space: "data",
121 access: "RW"
122 }],
123 ];
124 };
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