1 /*
2 * Copyright (c) 2010 by Texas Instruments and others.
3 * All rights reserved. This program and the accompanying materials
4 * are made available under the terms of the Eclipse Public License v1.0
5 * which accompanies this distribution, and is available at
6 * http://www.eclipse.org/legal/epl-v10.html
7 *
8 * Contributors:
9 * Texas Instruments - initial implementation
10 *
11 * */
12
13 /*
14 * ======== ITMS320C642x.xdc ========
15 *
16 */
17
18 /*!
19 * ======== ITMS320C642x ========
20 * The C642x device data sheet module.
21 *
22 * This module implements the ICpuDataSheet interface and is
23 * used by platforms to obtain "data sheet" information about this device.
24 */
25 metaonly interface ITMS320C642x inherits ti.catalog.ICpuDataSheet
26 {
27 config long cacheSizeL1[string] = [
28 ["0k", 0x0000],
29 ["4k", 0x1000],
30 ["8k", 0x2000],
31 ["16k", 0x4000],
32 ["32k", 0x8000],
33 ];
34
35 config long cacheSizeL2[string] = [
36 ["0k", 0x00000],
37 ["32k", 0x08000],
38 ["64k", 0x10000],
39 ["128k", 0x20000]
40 ];
41
42 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
43 ['l1PMode',{desc:"L1P Cache",
44 map : [["0k",0x0000],
45 ["4k",0x1000],
46 ["8k",0x2000],
47 ["16k",0x4000],
48 ["32k",0x8000]],
49 defaultValue: "0k",
50 memorySection: "L1PSRAM"}],
51
52 ['l1DMode',{desc:"L1D Cache",
53 map : [["0k",0x0000],
54 ["4k",0x1000],
55 ["8k",0x2000],
56 ["16k",0x4000],
57 ["32k",0x8000]],
58 defaultValue: "0k",
59 memorySection: "L1DSRAM"}],
60
61 ['l2Mode',{desc:"L2 Cache",
62 map : [["0k",0x0000],
63 ["32k",0x8000],
64 ["64k",0x10000],
65 ["128k",0x20000]],
66 defaultValue: "0k",
67 memorySection: "IRAM"}],
68
69 ];
70
71 instance:
72
73 override config string cpuCore = "64x+";
74 override config string isa = "64P";
75 override config string cpuCoreRevision = "1.0";
76
77 override config int minProgUnitSize = 1;
78 override config int minDataUnitSize = 1;
79 override config int dataWordSize = 4;
80
81 /*!
82 * ======== memMap ========
83 * The default memory map for this device
84 */
85 config xdc.platform.IPlatform.Memory memMap[string] = [
86 ["IRAM", {
87 comment: "Internal 128KB UMAP0 memory",
88 name: "IRAM",
89 base: 0x10800000,
90 len: 0x00020000,
91 space: "code/data",
92 access: "RWX"
93 }],
94
95 ["L1PSRAM", {
96 comment: "Internal 32KB RAM/CACHE L1 program memory",
97 name: "L1PSRAM",
98 base: 0x10E08000,
99 len: 0x00008000,
100 space: "code",
101 access: "RWX"
102 }],
103
104 ["L1DSRAM", {
105 comment: "Internal 80KB RAM/CACHE L1 data memory",
106 name: "L1DSRAM",
107 base: 0x10F04000,
108 len: 0x00014000,
109 space: "data",
110 access: "RW"
111 }],
112 ];
113 };
114 /*
115 * @(#) ti.catalog.c6000; 1, 0, 0, 0,276; 8-7-2010 18:18:08; /db/ztree/library/trees/platform/platform-l20x/src/
116 */
117