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13 14 15 16
17 package ti.catalog.c6000;
18
19 /*!
20 * ======== ITI8148 ========
21 * An interface implemented by all TI8148 devices
22 *
23 * This interface is defined to factor common data about all TI8148 type devices
24 * into a single place; they all have the same internal memory.
25 */
26 metaonly interface ITI8148 inherits ti.catalog.ICpuDataSheet
27 {
28
29 config long cacheSizeL1[string] = [
30 ["0k", 0x0000],
31 ["4k", 0x1000],
32 ["8k", 0x2000],
33 ["16k", 0x4000],
34 ["32k", 0x8000],
35 ];
36
37 config long cacheSizeL2[string] = [
38 ["0k", 0x00000],
39 ["32k", 0x08000],
40 ["64k", 0x10000],
41 ["128k",0x20000],
42 ["256k",0x40000],
43 ];
44
45 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
46 ['l1PMode',{desc:"L1P Cache",
47 map : [["0k",0x0000],
48 ["4k",0x1000],
49 ["8k",0x2000],
50 ["16k",0x4000],
51 ["32k",0x8000]],
52 defaultValue: "0k",
53 memorySection: "L1PSRAM"}],
54
55 ['l1DMode',{desc:"L1D Cache",
56 map : [["0k",0x0000],
57 ["4k",0x1000],
58 ["8k",0x2000],
59 ["16k",0x4000],
60 ["32k",0x8000]],
61 defaultValue: "0k",
62 memorySection: "L1DSRAM"}],
63
64 ['l2Mode',{desc:"L2 Cache",
65 map : [["0k",0x0000],
66 ["32k",0x8000],
67 ["64k",0x10000],
68 ["128k",0x20000],
69 ["256k",0x40000]],
70 defaultValue: "0k",
71 memorySection: "IRAM"}],
72
73 ];
74
75 instance:
76 config ti.catalog.peripherals.hdvicp2.HDVICP2.Instance hdvicp0;
77 config ti.catalog.peripherals.hdvicp2.HDVICP2.Instance hdvicp1;
78 config ti.catalog.peripherals.hdvicp2.HDVICP2.Instance hdvicp2;
79
80 override config int minProgUnitSize = 1;
81 override config int minDataUnitSize = 1;
82 override config int dataWordSize = 4;
83
84 override config string cpuCore = "674";
85 override config string isa = "674";
86 override config string cpuCoreRevision = "1.0";
87
88 config xdc.platform.IPlatform.Memory memMap[string] = [
89
90 ["IRAM", {
91 comment: "Internal 256KB L2 memory",
92 name: "IRAM",
93 base: 0x10800000,
94 len: 0x00040000,
95 space: "code/data",
96 access: "RWX"
97 }],
98
99 ["L1PSRAM", {
100 comment: "Internal 32KB L1 program memory",
101 name: "L1PSRAM",
102 base: 0x10E00000,
103 len: 0x00008000,
104 space: "code",
105 access: "RWX"
106 }],
107
108 ["L1DSRAM", {
109 comment: "Internal 32KB L1 data memory",
110 name: "L1DSRAM",
111 base: 0x10F00000,
112 len: 0x00008000,
113 space: "data",
114 access: "RW"
115 }],
116 ];
117 };
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121