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17 package ti.catalog.c6000;
18
19 /*!
20 * ======== IOMAP2x3x ========
21 * An interface implemented by all OMAP2x3x devices
22 *
23 * This interface is defined to factor common data about all OMAP2x3x devices
24 * into a single place; they all have the same internal memory.
25 */
26 metaonly interface IOMAP2x3x inherits ti.catalog.ICpuDataSheet
27 {
28
29 config long cacheSizeL1[string] = [
30 ["0k", 0x0000],
31 ["4k", 0x1000],
32 ["8k", 0x2000],
33 ["16k", 0x4000],
34 ["32k", 0x8000],
35 ];
36
37 config long cacheSizeL2[string] = [
38 ["0k", 0x00000],
39 ["32k", 0x08000],
40 ["64k", 0x10000]
41 ];
42
43 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
44 ['l1PMode',{desc:"L1P Cache",
45 map : [["0k",0x0000],
46 ["4k",0x1000],
47 ["8k",0x2000],
48 ["16k",0x4000],
49 ["32k",0x8000]],
50 defaultValue: "0k",
51 memorySection: "L1PSRAM"}],
52
53 ['l1DMode',{desc:"L1D Cache",
54 map : [["0k",0x0000],
55 ["4k",0x1000],
56 ["8k",0x2000],
57 ["16k",0x4000],
58 ["32k",0x8000]],
59 defaultValue: "0k",
60 memorySection: "L1DSRAM"}],
61
62 ['l2Mode',{desc:"L2 Cache",
63 map : [["0k",0x0000],
64 ["32k",0x8000],
65 ["64k",0x10000]],
66 defaultValue: "0k",
67 memorySection: "IRAM"}],
68
69 ];
70
71 instance:
72 override config int minProgUnitSize = 1;
73 override config int minDataUnitSize = 1;
74 override config int dataWordSize = 4;
75
76 override config string cpuCore = "64x+";
77 override config string isa = "64P";
78
79 config xdc.platform.IPlatform.Memory memMap[string] = [
80 ["IRAM", {
81 comment: "Internal 64KB L2 UMAP0 memory",
82 name: "IRAM",
83 base: 0x10800000,
84 len: 0x00010000,
85 space: "code/data",
86 access: "RWX"
87 }],
88
89 ["L1PSRAM", {
90 comment: "Internal 32KB L1 program memory",
91 name: "L1PSRAM",
92 base: 0x10E00000,
93 len: 0x00008000,
94 space: "code",
95 access: "RWX"
96 }],
97
98 ["L1DSRAM", {
99 comment: "Internal 80KB L1 data memory",
100 name: "L1DSRAM",
101 base: 0x10F04000,
102 len: 0x00014000,
103 space: "data",
104 access: "RW"
105 }],
106 ];
107 };
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