1    /*
     2     *  Copyright (c) 2010 by Texas Instruments and others.
     3     *  All rights reserved. This program and the accompanying materials
     4     *  are made available under the terms of the Eclipse Public License v1.0
     5     *  which accompanies this distribution, and is available at
     6     *  http://www.eclipse.org/legal/epl-v10.html
     7     *
     8     *  Contributors:
     9     *      Texas Instruments - initial implementation
    10     *
    11     * */
    12    
    13    /*
    14     *  ======== ICacheInfo.xdc ========
    15     */
    16    
    17    
    18    package ti.catalog.c6000;
    19    
    20    metaonly interface ICacheInfo {
    21        /*!
    22         *  ======== CacheDesc ========
    23         *  Structure used by ICpuDataSheet implementations to
    24         *  specify device cache modes. 
    25         *   
    26         *  A map is defined by an ICpuDataSheet implementation
    27         *  that maps a string denoting a device register setting
    28         *  to a CacheDesc structure. This maybe used in implementing
    29         *  the 'getMemoryMap' method. An example of such a map is shown below :
    30         *
    31         *   readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] =  [
    32             *    ['l1PMode',{desc:"L1P Cache",
    33             *                map : [["0k",0x0000],
    34             *                       ["4k",0x1000],
    35             *                       ["8k",0x2000],
    36             *                       ["16k",0x4000],
    37             *                       ["32k",0x8000]],
    38             *                defaultValue: "0k",
    39             *                memorySection: "L1PSRAM"}],
    40             *
    41             *        ['l1DMode',{desc:"L1D Cache",
    42             *                map : [["0k",0x0000],
    43             *                       ["4k",0x1000],
    44             *                       ["8k",0x2000],
    45             *                       ["16k",0x4000],
    46             *                       ["32k",0x8000]],
    47             *                defaultValue: "0k",
    48             *                memorySection: "L1DSRAM"}],
    49             *            
    50             *    ['l2Mode',{desc:"L2 Cache",
    51             *                map : [["0k",0x0000],
    52             *                       ["32k",0x8000],
    53             *                       ["64k",0x10000],
    54             *                       ["128k",0x20000],
    55             *                       ["256k",0x40000]],
    56             *                defaultValue: "0k",
    57             *                memorySection: "IRAM"}], 
    58         *
    59         *   ];
    60         *
    61         *  @_nodoc
    62         */
    63        struct CacheDesc {
    64            string desc;          /*! String describing the register setting */
    65            unsigned map[string]; /*! A hash of cache modes to cache size*/
    66            string defaultValue;  /*! The default cache mode for the device */
    67            string memorySection; /*! The associated memory section */
    68        };
    69    
    70    
    71    }
    72    /*
    73     *  @(#) ti.catalog.c6000; 1, 0, 0, 0,276; 8-7-2010 18:18:08; /db/ztree/library/trees/platform/platform-l20x/src/
    74     */
    75