1 /*
2 * Copyright (c) 2010 by Texas Instruments and others.
3 * All rights reserved. This program and the accompanying materials
4 * are made available under the terms of the Eclipse Public License v1.0
5 * which accompanies this distribution, and is available at
6 * http://www.eclipse.org/legal/epl-v10.html
7 *
8 * Contributors:
9 * Texas Instruments - initial implementation
10 *
11 * */
12
13 /*
14 * ======== Boot.xdc ========
15 *
16 */
17
18 package ti.catalog.arm.cortexm3.lm3init;
19
20 import xdc.rov.ViewInfo;
21
22 @Template("./Boot.xdt")
23
24 metaonly module Boot
25 {
26 metaonly struct ModuleView {
27 Bool configureClock;
28 Bool sysClockDivEnable;
29 String sysClockDiv;
30 Bool pwmClockDivEnable;
31 String pwmClockDiv;
32 String xtal;
33 String oscSrc;
34 Bool pllBypass;
35 Bool pllOutEnable;
36 Bool ioscDisable;
37 Bool moscDisable;
38 Bool configureLdo;
39 String ldoOut;
40 }
41
42 @Facet
43 metaonly config ViewInfo.Instance rovViewInfo =
44 ViewInfo.create({
45 viewMap: [
46 [
47 'Module',
48 {
49 type: ViewInfo.MODULE,
50 viewInitFxn: 'viewInitModule',
51 structName: 'ModuleView'
52 }
53 ],
54 ]
55 });
56
57
58 enum SysDiv {
59 SYSDIV_1 = 0x07800000, /* Processor clock is osc/pll /1 */
60 SYSDIV_2 = 0x00C00000, /* Processor clock is osc/pll /2 */
61 SYSDIV_3 = 0x01400000, /* Processor clock is osc/pll /3 */
62 SYSDIV_4 = 0x01C00000, /* Processor clock is osc/pll /4 */
63 SYSDIV_5 = 0x02400000, /* Processor clock is osc/pll /5 */
64 SYSDIV_6 = 0x02C00000, /* Processor clock is osc/pll /6 */
65 SYSDIV_7 = 0x03400000, /* Processor clock is osc/pll /7 */
66 SYSDIV_8 = 0x03C00000, /* Processor clock is osc/pll /8 */
67 SYSDIV_9 = 0x04400000, /* Processor clock is osc/pll /9 */
68 SYSDIV_10 = 0x04C00000, /* Processor clock is osc/pll /10 */
69 SYSDIV_11 = 0x05400000, /* Processor clock is osc/pll /11 */
70 SYSDIV_12 = 0x05C00000, /* Processor clock is osc/pll /12 */
71 SYSDIV_13 = 0x06400000, /* Processor clock is osc/pll /13 */
72 SYSDIV_14 = 0x06C00000, /* Processor clock is osc/pll /14 */
73 SYSDIV_15 = 0x07400000, /* Processor clock is osc/pll /15 */
74 SYSDIV_16 = 0x07C00000, /* Processor clock is osc/pll /16 */
75 SYSDIV_17 = 0x88400000, /* Processor clock is osc/pll /17 */
76 SYSDIV_18 = 0x88C00000, /* Processor clock is osc/pll /18 */
77 SYSDIV_19 = 0x89400000, /* Processor clock is osc/pll /19 */
78 SYSDIV_20 = 0x89C00000, /* Processor clock is osc/pll /20 */
79 SYSDIV_21 = 0x8A400000, /* Processor clock is osc/pll /21 */
80 SYSDIV_22 = 0x8AC00000, /* Processor clock is osc/pll /22 */
81 SYSDIV_23 = 0x8B400000, /* Processor clock is osc/pll /23 */
82 SYSDIV_24 = 0x8BC00000, /* Processor clock is osc/pll /24 */
83 SYSDIV_25 = 0x8C400000, /* Processor clock is osc/pll /25 */
84 SYSDIV_26 = 0x8CC00000, /* Processor clock is osc/pll /26 */
85 SYSDIV_27 = 0x8D400000, /* Processor clock is osc/pll /27 */
86 SYSDIV_28 = 0x8DC00000, /* Processor clock is osc/pll /28 */
87 SYSDIV_29 = 0x8E400000, /* Processor clock is osc/pll /29 */
88 SYSDIV_30 = 0x8EC00000, /* Processor clock is osc/pll /30 */
89 SYSDIV_31 = 0x8F400000, /* Processor clock is osc/pll /31 */
90 SYSDIV_32 = 0x8FC00000, /* Processor clock is osc/pll /32 */
91 SYSDIV_33 = 0x90400000, /* Processor clock is osc/pll /33 */
92 SYSDIV_34 = 0x90C00000, /* Processor clock is osc/pll /34 */
93 SYSDIV_35 = 0x91400000, /* Processor clock is osc/pll /35 */
94 SYSDIV_36 = 0x91C00000, /* Processor clock is osc/pll /36 */
95 SYSDIV_37 = 0x92400000, /* Processor clock is osc/pll /37 */
96 SYSDIV_38 = 0x92C00000, /* Processor clock is osc/pll /38 */
97 SYSDIV_39 = 0x93400000, /* Processor clock is osc/pll /39 */
98 SYSDIV_40 = 0x93C00000, /* Processor clock is osc/pll /40 */
99 SYSDIV_41 = 0x94400000, /* Processor clock is osc/pll /41 */
100 SYSDIV_42 = 0x94C00000, /* Processor clock is osc/pll /42 */
101 SYSDIV_43 = 0x95400000, /* Processor clock is osc/pll /43 */
102 SYSDIV_44 = 0x95C00000, /* Processor clock is osc/pll /44 */
103 SYSDIV_45 = 0x96400000, /* Processor clock is osc/pll /45 */
104 SYSDIV_46 = 0x96C00000, /* Processor clock is osc/pll /46 */
105 SYSDIV_47 = 0x97400000, /* Processor clock is osc/pll /47 */
106 SYSDIV_48 = 0x97C00000, /* Processor clock is osc/pll /48 */
107 SYSDIV_49 = 0x98400000, /* Processor clock is osc/pll /49 */
108 SYSDIV_50 = 0x98C00000, /* Processor clock is osc/pll /50 */
109 SYSDIV_51 = 0x99400000, /* Processor clock is osc/pll /51 */
110 SYSDIV_52 = 0x99C00000, /* Processor clock is osc/pll /52 */
111 SYSDIV_53 = 0x9A400000, /* Processor clock is osc/pll /53 */
112 SYSDIV_54 = 0x9AC00000, /* Processor clock is osc/pll /54 */
113 SYSDIV_55 = 0x9B400000, /* Processor clock is osc/pll /55 */
114 SYSDIV_56 = 0x9BC00000, /* Processor clock is osc/pll /56 */
115 SYSDIV_57 = 0x9C400000, /* Processor clock is osc/pll /57 */
116 SYSDIV_58 = 0x9CC00000, /* Processor clock is osc/pll /58 */
117 SYSDIV_59 = 0x9D400000, /* Processor clock is osc/pll /59 */
118 SYSDIV_60 = 0x9DC00000, /* Processor clock is osc/pll /60 */
119 SYSDIV_61 = 0x9E400000, /* Processor clock is osc/pll /61 */
120 SYSDIV_62 = 0x9EC00000, /* Processor clock is osc/pll /62 */
121 SYSDIV_63 = 0x9F400000, /* Processor clock is osc/pll /63 */
122 SYSDIV_64 = 0x9FC00000, /* Processor clock is osc/pll /64 */
123 SYSDIV_2_5 = 0xC1000000, /* Processor clock is pll / 2.5 */
124 SYSDIV_3_5 = 0xC1800000, /* Processor clock is pll / 3.5 */
125 SYSDIV_4_5 = 0xC2000000, /* Processor clock is pll / 4.5 */
126 SYSDIV_5_5 = 0xC2800000, /* Processor clock is pll / 5.5 */
127 SYSDIV_6_5 = 0xC3000000, /* Processor clock is pll / 6.5 */
128 SYSDIV_7_5 = 0xC3800000, /* Processor clock is pll / 7.5 */
129 SYSDIV_8_5 = 0xC4000000, /* Processor clock is pll / 8.5 */
130 SYSDIV_9_5 = 0xC4800000, /* Processor clock is pll / 9.5 */
131 SYSDIV_10_5 = 0xC5000000, /* Processor clock is pll / 10.5 */
132 SYSDIV_11_5 = 0xC5800000, /* Processor clock is pll / 11.5 */
133 SYSDIV_12_5 = 0xC6000000, /* Processor clock is pll / 12.5 */
134 SYSDIV_13_5 = 0xC6800000, /* Processor clock is pll / 13.5 */
135 SYSDIV_14_5 = 0xC7000000, /* Processor clock is pll / 14.5 */
136 SYSDIV_15_5 = 0xC7800000, /* Processor clock is pll / 15.5 */
137 SYSDIV_16_5 = 0xC8000000, /* Processor clock is pll / 16.5 */
138 SYSDIV_17_5 = 0xC8800000, /* Processor clock is pll / 17.5 */
139 SYSDIV_18_5 = 0xC9000000, /* Processor clock is pll / 18.5 */
140 SYSDIV_19_5 = 0xC9800000, /* Processor clock is pll / 19.5 */
141 SYSDIV_20_5 = 0xCA000000, /* Processor clock is pll / 20.5 */
142 SYSDIV_21_5 = 0xCA800000, /* Processor clock is pll / 21.5 */
143 SYSDIV_22_5 = 0xCB000000, /* Processor clock is pll / 22.5 */
144 SYSDIV_23_5 = 0xCB800000, /* Processor clock is pll / 23.5 */
145 SYSDIV_24_5 = 0xCC000000, /* Processor clock is pll / 24.5 */
146 SYSDIV_25_5 = 0xCC800000, /* Processor clock is pll / 25.5 */
147 SYSDIV_26_5 = 0xCD000000, /* Processor clock is pll / 26.5 */
148 SYSDIV_27_5 = 0xCD800000, /* Processor clock is pll / 27.5 */
149 SYSDIV_28_5 = 0xCE000000, /* Processor clock is pll / 28.5 */
150 SYSDIV_29_5 = 0xCE800000, /* Processor clock is pll / 29.5 */
151 SYSDIV_30_5 = 0xCF000000, /* Processor clock is pll / 30.5 */
152 SYSDIV_31_5 = 0xCF800000, /* Processor clock is pll / 31.5 */
153 SYSDIV_32_5 = 0xD0000000, /* Processor clock is pll / 32.5 */
154 SYSDIV_33_5 = 0xD0800000, /* Processor clock is pll / 33.5 */
155 SYSDIV_34_5 = 0xD1000000, /* Processor clock is pll / 34.5 */
156 SYSDIV_35_5 = 0xD1800000, /* Processor clock is pll / 35.5 */
157 SYSDIV_36_5 = 0xD2000000, /* Processor clock is pll / 36.5 */
158 SYSDIV_37_5 = 0xD2800000, /* Processor clock is pll / 37.5 */
159 SYSDIV_38_5 = 0xD3000000, /* Processor clock is pll / 38.5 */
160 SYSDIV_39_5 = 0xD3800000, /* Processor clock is pll / 39.5 */
161 SYSDIV_40_5 = 0xD4000000, /* Processor clock is pll / 40.5 */
162 SYSDIV_41_5 = 0xD4800000, /* Processor clock is pll / 41.5 */
163 SYSDIV_42_5 = 0xD5000000, /* Processor clock is pll / 42.5 */
164 SYSDIV_43_5 = 0xD5800000, /* Processor clock is pll / 43.5 */
165 SYSDIV_44_5 = 0xD6000000, /* Processor clock is pll / 44.5 */
166 SYSDIV_45_5 = 0xD6800000, /* Processor clock is pll / 45.5 */
167 SYSDIV_46_5 = 0xD7000000, /* Processor clock is pll / 46.5 */
168 SYSDIV_47_5 = 0xD7800000, /* Processor clock is pll / 47.5 */
169 SYSDIV_48_5 = 0xD8000000, /* Processor clock is pll / 48.5 */
170 SYSDIV_49_5 = 0xD8800000, /* Processor clock is pll / 49.5 */
171 SYSDIV_50_5 = 0xD9000000, /* Processor clock is pll / 50.5 */
172 SYSDIV_51_5 = 0xD9800000, /* Processor clock is pll / 51.5 */
173 SYSDIV_52_5 = 0xDA000000, /* Processor clock is pll / 52.5 */
174 SYSDIV_53_5 = 0xDA800000, /* Processor clock is pll / 53.5 */
175 SYSDIV_54_5 = 0xDB000000, /* Processor clock is pll / 54.5 */
176 SYSDIV_55_5 = 0xDB800000, /* Processor clock is pll / 55.5 */
177 SYSDIV_56_5 = 0xDC000000, /* Processor clock is pll / 56.5 */
178 SYSDIV_57_5 = 0xDC800000, /* Processor clock is pll / 57.5 */
179 SYSDIV_58_5 = 0xDD000000, /* Processor clock is pll / 58.5 */
180 SYSDIV_59_5 = 0xDD800000, /* Processor clock is pll / 59.5 */
181 SYSDIV_60_5 = 0xDE000000, /* Processor clock is pll / 60.5 */
182 SYSDIV_61_5 = 0xDE800000, /* Processor clock is pll / 61.5 */
183 SYSDIV_62_5 = 0xDF000000, /* Processor clock is pll / 62.5 */
184 SYSDIV_63_5 = 0xDF800000 /* Processor clock is pll / 63.5 */
185 }
186
187 enum PwmDiv {
188 PWMDIV_1 = 0x00000000, /* PWM clock /1 */
189 PWMDIV_2 = 0x00100000, /* PWM clock /2 */
190 PWMDIV_4 = 0x00120000, /* PWM clock /4 */
191 PWMDIV_8 = 0x00140000, /* PWM clock /8 */
192 PWMDIV_16 = 0x00160000, /* PWM clock /16 */
193 PWMDIV_32 = 0x00180000, /* PWM clock /32 */
194 PWMDIV_64 = 0x001A0000 /* PWM clock /64 */
195 }
196
197 enum XtalFreq {
198 XTAL_1MHZ = 0x00000000, /* Using a 1MHz crystal */
199 XTAL_1_84MHZ = 0x00000040, /* Using a 1.8432MHz crystal */
200 XTAL_2MHZ = 0x00000080, /* Using a 2MHz crystal */
201 XTAL_2_45MHZ = 0x000000C0, /* Using a 2.4576MHz crystal */
202 XTAL_3_57MHZ = 0x00000100, /* Using a 3.579545MHz crystal */
203 XTAL_3_68MHZ = 0x00000140, /* Using a 3.6864MHz crystal */
204 XTAL_4MHZ = 0x00000180, /* Using a 4MHz crystal */
205 XTAL_4_09MHZ = 0x000001C0, /* Using a 4.096MHz crystal */
206 XTAL_4_91MHZ = 0x00000200, /* Using a 4.9152MHz crystal */
207 XTAL_5MHZ = 0x00000240, /* Using a 5MHz crystal */
208 XTAL_5_12MHZ = 0x00000280, /* Using a 5.12MHz crystal */
209 XTAL_6MHZ = 0x000002C0, /* Using a 6MHz crystal */
210 XTAL_6_14MHZ = 0x00000300, /* Using a 6.144MHz crystal */
211 XTAL_7_37MHZ = 0x00000340, /* Using a 7.3728MHz crystal */
212 XTAL_8MHZ = 0x00000380, /* Using a 8MHz crystal */
213 XTAL_8_19MHZ = 0x000003C0, /* Using a 8.192MHz crystal */
214 XTAL_10MHZ = 0x00000400, /* 10.0 MHz (USB) */
215 XTAL_12MHZ = 0x00000440, /* 12.0 MHz (USB) */
216 XTAL_12_2MHZ = 0x00000480, /* 12.288 MHz */
217 XTAL_13_5MHZ = 0x000004C0, /* 13.56 MHz */
218 XTAL_14_3MHZ = 0x00000500, /* 14.31818 MHz */
219 XTAL_16MHZ = 0x00000540, /* 16.0 MHz (USB) */
220 XTAL_16_3MHZ = 0x00000580 /* 16.384 MHz */
221 }
222
223 enum OscSrc {
224 OSCSRC_MAIN = 0x00000000, /* Use the main oscillator */
225 OSCSRC_INT = 0x00000010, /* Use the internal oscillator */
226 OSCSRC_INT4 = 0x00000020, /* Use the internal oscillator / 4 */
227 OSCSRC_30 = 0x00000030 /* 30 KHz internal oscillator */
228 }
229
230 enum LdoOut {
231 LDOPCTL_2_55V = 0x0000001F, /* LDO output of 2.55V */
232 LDOPCTL_2_60V = 0x0000001E, /* LDO output of 2.60V */
233 LDOPCTL_2_65V = 0x0000001D, /* LDO output of 2.65V */
234 LDOPCTL_2_70V = 0x0000001C, /* LDO output of 2.70V */
235 LDOPCTL_2_75V = 0x0000001B, /* LDO output of 2.75V */
236 LDOPCTL_2_25V = 0x00000005, /* LDO output of 2.25V */
237 LDOPCTL_2_30V = 0x00000004, /* LDO output of 2.30V */
238 LDOPCTL_2_35V = 0x00000003, /* LDO output of 2.35V */
239 LDOPCTL_2_40V = 0x00000002, /* LDO output of 2.40V */
240 LDOPCTL_2_45V = 0x00000001, /* LDO output of 2.45V */
241 LDOPCTL_2_50V = 0x00000000 /* LDO output of 2.50V */
242 }
243
244 /*!
245 * Clock configuration flag, default is false.
246 *
247 * Set to true to automatically configure the Clock.
248 */
249 config Bool configureClock = false;
250
251 /*! SYS Clock Divisor */
252 config SysDiv sysClockDiv = SYSDIV_1;
253
254 /*! PWM Clock Divisor */
255 config PwmDiv pwmClockDiv = PWMDIV_1;
256
257 /*! Crystal Value */
258 config XtalFreq xtal = XTAL_1MHZ;
259
260 /*! Oscillator Source */
261 config OscSrc oscSrc = OSCSRC_MAIN;
262
263 /*! PLL Bypass flag */
264 config Bool pllBypass = false;
265
266 /*! PLL Output Enable flag */
267 config Bool pllOutEnable = false;
268
269 /*! Internal Oscillator Disable flag */
270 config Bool ioscDisable = false;
271
272 /*! Main Oscillator Disable flag */
273 config Bool moscDisable = false;
274
275 /*!
276 * LDO configuration flag, default is false.
277 *
278 * Set to true to automatically configure the LDO.
279 */
280 config Bool configureLdo = false;
281
282 /*!
283 * LDO VADJ setting, default is 2.5V
284 */
285 config LdoOut ldoOut = LDOPCTL_2_50V;
286
287 /*!
288 * Code section that Boot module code is in.
289 *
290 * To place this section into a memory segment yourself, add the
291 * following to you configuration file:
292 *
293 * @p(code)
294 * Program.sectMap[Boot.bootCodeSection] = new Program.SectionSpec();
295 * Program.sectMap[Boot.bootCodeSection].loadSegment = "yourBootCodeMemorySegment";
296 * @p
297 *
298 * or to place the code at a specific address:
299 *
300 * @p(code)
301 * Program.sectMap[Boot.bootCodeSection] = new Program.SectionSpec();
302 * Program.sectMap[Boot.bootCodeSection].loadAdress = yourBootCodeAddress;
303 * @p
304 *
305 */
306 readonly config String bootCodeSection = ".bootCodeSection";
307
308 /*!
309 * @_nodoc
310 * computed RCC value based on settings
311 */
312 config UInt ulConfig;
313 };
314 /*
315 * @(#) ti.catalog.arm.cortexm3.lm3init; 1, 0, 0,34; 8-7-2010 18:17:55; /db/ztree/library/trees/platform/platform-l20x/src/
316 */
317