1 /*
2 * Copyright (c) 2008 Texas Instruments. All rights reserved.
3 * This program and the accompanying materials are made available under the
4 * terms of the Eclipse Public License v1.0 and Eclipse Distribution License
5 * v. 1.0 which accompanies this distribution. The Eclipse Public License is
6 * available at http://www.eclipse.org/legal/epl-v10.html and the Eclipse
7 * Distribution License is available at
8 * http://www.eclipse.org/org/documents/edl-v10.php.
9 *
10 * Contributors:
11 * Texas Instruments - initial implementation
12 * */
13 /*
14 * ======== ICacheSupport.xdc ========
15 */
16
17 import xdc.runtime.Error;
18
19 /*!
20 * ======== ICacheSupport ========
21 * Interface for OS specific back-end.
22 *
23 * The {@link xdc.runtime.knl} package contains modules that provide typical
24 * OS services. These xdc.runtime.knl modules require proxies to be
25 * bound to an OS specific delegate. This specifies the interface to
26 * be implemented by the OS specific delegate for
27 * {@link xdc.runtime.knl#Cache} module.
28 *
29 */
30
31 interface ICacheSupport
32 {
33 /*!
34 * ======== inv ========
35 * Invalidates range of memory.
36 *
37 * Invalidate the range of memory within the specified starting
38 * address and byte count. The range of addresses operated on
39 * gets quantized to whole cache lines in each cache. All lines
40 * in range are invalidated for all the 'type' caches.
41 *
42 * @param(blockPtr) start address of range to be invalidated
43 * @param(byteCnt) number of bytes to be invalidated
44 * @param(wait) wait until the operation is completed
45 * @param(eb) error block
46 * @a(returns) true for success; false for error.
47 */
48 Bool inv(Ptr blockPtr, SizeT byteCnt, Bool wait, Error.Block *eb);
49
50 /*!
51 * ======== wb ========
52 * Writes a range of memory from all cache(s)
53 *
54 * Writes the range of memory within the specified starting
55 * address and byte count. The range of addresses operated on
56 * gets quantized to whole cache lines in each cache. All lines
57 * within the range are left valid in the 'type' caches and the data
58 * within the range will be written to the source memory.
59 *
60 * @param(blockPtr) start address of range to be invalidated
61 * @param(byteCnt) number of bytes to be invalidated
62 * @param(wait) wait until the operation is completed
63 * @param(eb) error block
64 * @a(returns) true for success; false for error.
65 */
66 Bool wb(Ptr blockPtr, SizeT byteCnt, Bool wait, Error.Block *eb);
67
68 /*!
69 * ======== wbInv ========
70 * Writes back and invalidates range fo memory.
71 *
72 * Writes and invalidates the range of memory within the
73 * specified starting address and byte count. The range of
74 * addresses operated on gets quantized to whole cache lines in
75 * each cache. All lines within the range are written to the
76 * source memory and then invalidated for all 'type' caches.
77 *
78 * @param(blockPtr) start address of range to be invalidated
79 * @param(byteCnt) number of bytes to be invalidated
80 * @param(wait) wait until the operation is completed
81 * @param(eb) error block
82 * @a(returns) true for success; false for error.
83 */
84 Bool wbInv(Ptr blockPtr, SizeT byteCnt, Bool wait, Error.Block *eb);
85
86 /*!
87 * ======== wait ========
88 * Wait for a previous cache operation to complete
89 *
90 * Wait for the cache wb/wbInv/inv operation to complete. A cache
91 * operation is not truly complete until it has worked its way
92 * through all buffering and all memory writes have landed in the
93 * source memory.
94 *
95 * @a(returns) true for success; false for error.
96 */
97 Bool wait(Error.Block *eb);
98
99 }
100 /*
101 * @(#) xdc.runtime.knl; 1, 0, 0,97; 8-6-2010 17:20:31; /db/ztree/library/trees/xdc/xdc-v47x/src/packages/
102 */
103