1 /*
2 * Copyright (c) 2008 Texas Instruments. All rights reserved.
3 * This program and the accompanying materials are made available under the
4 * terms of the Eclipse Public License v1.0 and Eclipse Distribution License
5 * v. 1.0 which accompanies this distribution. The Eclipse Public License is
6 * available at http://www.eclipse.org/legal/epl-v10.html and the Eclipse
7 * Distribution License is available at
8 * http://www.eclipse.org/org/documents/edl-v10.php.
9 *
10 * Contributors:
11 * Texas Instruments - initial implementation
12 * */
13 /*
14 * ======== Cache.xdc ========
15 */
16
17 import xdc.runtime.Error;
18 import xdc.runtime.knl.ICacheSupport;
19
20 /*!
21 * ======== Cache ========
22 * Cache Services
23 *
24 * The Cache module provide APIs to allow applications to maintain cache
25 * coherency.
26 *
27 * This module will use an OS specific delegate (back-end) to manipulate the
28 * cache.
29 * This module has a module wide config parameter {@link #Proxy} which needs to
30 * be bound to an OS specific delegate before this module can be used.
31 *
32 * Here is an example showing how the proxy is bound to an BIOS 6.x specific
33 * delegate.
34 *
35 * @p(code) 36 * var Cache = xdc.useModule('xdc.runtime.knl.Cache');
37 * Cache.Proxy = xdc.useModule('ti.sysbios.xdcruntime.CacheSupport');
38 * @p 39 *
40 * Typically the package containing the delegates have a Settings module that
41 * will bind all {@link xdc.runtime.knl} proxies. The following
42 * example sets up all the xdc.runtime.knl proxies.
43 *
44 * @p(code) 45 * xdc.useModule("ti.sysbios.xdcruntime.Settings");
46 * @p 47 */
48
49 module Cache
50 {
51 /*!
52 * ======== Proxy ========
53 * ICacheSupport proxy
54 *
55 * Cache will use this proxy to access the cache hardware using
56 * OS specific APIs.
57 */
58 proxy Proxy inherits ICacheSupport;
59
60 /*!
61 * ======== inv ========
62 * Invalidate range of memory for all cache(s)
63 *
64 * Invalidate the range of memory within the specified starting
65 * address and byte count. The range of addresses operated on
66 * gets quantized to whole cache lines in each cache. All lines
67 * in range are invalidated for all cache types.
68 *
69 * @param(blockPtr) start address of range to be invalidated
70 * @param(byteCnt) number of bytes to be invalidated
71 * @param(wait) wait until the operation is completed
72 * @param(eb) error block
73 * @a(returns) true for success; false for error.
74 */
75 Bool inv(Ptr blockPtr, SizeT byteCnt, Bool wait, Error.Block *eb);
76
77 /*!
78 * ======== wb ========
79 * Writes back a range of memory from all cache(s)
80 *
81 * Writes back the range of memory within the specified starting
82 * address and byte count. The range of addresses operated on
83 * gets quantized to whole cache lines in each cache. All lines
84 * within the range are left valid in all caches and the data
85 * within the range will be written back to the source memory.
86 *
87 * @param(blockPtr) start address of range to be invalidated
88 * @param(byteCnt) number of bytes to be invalidated
89 * @param(wait) wait until the operation is completed
90 * @param(eb) error block
91 * @a(returns) true for success; false for error.
92 */
93 Bool wb(Ptr blockPtr, SizeT byteCnt, Bool wait, Error.Block *eb);
94
95 /*!
96 * ======== wbInv ========
97 * Write back and invalidate range of memory.
98 *
99 * Writes back and invalidates the range of memory within the
100 * specified starting address and byte count. The range of
101 * addresses operated on gets quantized to whole cache lines in
102 * each cache. All lines within the range are written back to the
103 * source memory and then invalidated for all cache types.
104 *
105 * @param(blockPtr) start address of range to be invalidated
106 * @param(byteCnt) number of bytes to be invalidated
107 * @param(wait) wait until the operation is completed
108 * @param(eb) error block
109 * @a(returns) true for success; false for error.
110 */
111 Bool wbInv(Ptr blockPtr, SizeT byteCnt, Bool wait, Error.Block *eb);
112
113 /*!
114 * ======== wait ========
115 * Wait for a previous cache operation to complete
116 *
117 * Wait for the cache wb/wbInv/inv operation to complete. A cache
118 * operation is not truly complete until it has worked its way
119 * through all buffering and all memory writes have landed in the
120 * source memory.
121 *
122 * @param(eb) error block
123 * @a(returns) true for success; false for error.
124 */
125 Bool wait(Error.Block *eb);
126 }
127 /*
128 * @(#) xdc.runtime.knl; 1, 0, 0,97; 8-6-2010 17:20:31; /db/ztree/library/trees/xdc/xdc-v47x/src/packages/
129 */
130