1    /*
     2     *  Copyright (c) 2010 by Texas Instruments and others.
     3     *  All rights reserved. This program and the accompanying materials
     4     *  are made available under the terms of the Eclipse Public License v1.0
     5     *  which accompanies this distribution, and is available at
     6     *  http://www.eclipse.org/legal/epl-v10.html
     7     *
     8     *  Contributors:
     9     *      Texas Instruments - initial implementation
    10     *
    11     * */
    12    
    13    /*
    14     *  ======== IOMAP3xxx.xdc ========
    15     *
    16     */
    17    package ti.catalog.c6000;
    18    
    19    /*!
    20     *  ======== IOMAP3xxx ========
    21     *  An interface implemented by all OMAP3xxx devices
    22     *
    23     *  This interface is defined to factor common data about all OMAP3xxx devices
    24     *  into a single place; they all have the same internal memory.
    25     */
    26    metaonly interface IOMAP3xxx inherits ti.catalog.ICpuDataSheet
    27    {
    28    
    29        config long cacheSizeL1[string] = [
    30            ["0k",  0x0000],
    31            ["4k",  0x1000],
    32            ["8k",  0x2000],
    33            ["16k", 0x4000],
    34            ["32k", 0x8000],
    35        ];
    36    
    37        config long cacheSizeL2[string] = [
    38            ["0k",  0x00000],
    39            ["32k", 0x08000],
    40            ["64k", 0x10000]
    41        ];
    42    
    43       readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] =  [
    44                 ['l1PMode',{desc:"L1P Cache",
    45                             map : [["0k",0x0000],
    46                                    ["4k",0x1000],
    47                                    ["8k",0x2000],
    48                                    ["16k",0x4000],
    49                                    ["32k",0x8000]],
    50                             defaultValue: "0k",
    51                             memorySection: "L1PSRAM"}],
    52             
    53                     ['l1DMode',{desc:"L1D Cache",
    54                             map : [["0k",0x0000],
    55                                    ["4k",0x1000],
    56                                    ["8k",0x2000],
    57                                    ["16k",0x4000],
    58                                    ["32k",0x8000]],
    59                             defaultValue: "0k",
    60                             memorySection: "L1DSRAM"}],
    61                         
    62                 ['l2Mode',{desc:"L2 Cache",
    63                             map : [["0k",0x0000],
    64                                    ["32k",0x8000],
    65                                    ["64k",0x10000]],
    66                             defaultValue: "0k",
    67                             memorySection: "IRAM"}], 
    68    
    69        ];    
    70    
    71    instance:
    72        override config int     minProgUnitSize = 1;
    73        override config int     minDataUnitSize = 1;    
    74        override config int     dataWordSize    = 4;
    75    
    76        override config string   cpuCore        = "64x+";
    77        override config string   isa = "64P";
    78    
    79        config xdc.platform.IPlatform.Memory memMap[string]  = [
    80            ["IRAM", {
    81                comment:    "Internal 96KB L2 UMAP0 memory",
    82                name:       "IRAM",
    83                base:       0x107F8000,
    84                len:        0x00018000,
    85                space:      "code/data",
    86                access:     "RWX"
    87            }],
    88            
    89            ["L1PSRAM", {
    90                comment:    "Internal 32KB L1 program memory",
    91                name:       "L1PSRAM",
    92                base:       0x10E00000,
    93                len:        0x00008000,
    94                space:      "code",
    95                access:     "RWX"
    96            }],
    97    
    98            ["L1DSRAM", {
    99                comment:    "Internal 80KB L1 data memory",
   100                name:       "L1DSRAM",
   101                base:       0x10F04000,
   102                len:        0x00014000,
   103                space:      "data",
   104                access:     "RW"
   105            }],
   106        ];
   107    };
   108    /*
   109     *  @(#) ti.catalog.c6000; 1, 0, 0, 0,276; 8-7-2010 18:18:08; /db/ztree/library/trees/platform/platform-l20x/src/
   110     */
   111