1 /*
2 * Copyright (c) 2010 by Texas Instruments and others.
3 * All rights reserved. This program and the accompanying materials
4 * are made available under the terms of the Eclipse Public License v1.0
5 * which accompanies this distribution, and is available at
6 * http://www.eclipse.org/legal/epl-v10.html
7 *
8 * Contributors:
9 * Texas Instruments - initial implementation
10 *
11 * */
12
13 /*
14 * ======== IDaVinci.xdc ========
15 *
16 */
17 package ti.catalog.c6000;
18
19 /*!
20 * ======== IDaVinci ========
21 * An interface implemented by all DaVinci devices
22 *
23 * This interface is defined to factor common data about all DaVinci devices
24 * into a single place; they are all the same from the configuration point of
25 * view.
26 */
27 metaonly interface IDaVinci inherits ti.catalog.ICpuDataSheet
28 {
29 config long cacheSizeL1[string] = [
30 ["0k", 0x0000],
31 ["4k", 0x1000],
32 ["8k", 0x2000],
33 ["16k", 0x4000],
34 ["32k", 0x8000],
35 ];
36
37 config long cacheSizeL2[string] = [
38 ["0k", 0x00000],
39 ["32k", 0x08000],
40 ["64k", 0x10000]
41 ];
42
43 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
44 ['l1PMode',{desc:"L1P Cache",
45 map : [["0k",0x0000],
46 ["4k",0x1000],
47 ["8k",0x2000],
48 ["16k",0x4000],
49 ["32k",0x8000]],
50 defaultValue: "0k",
51 memorySection: "L1PSRAM"}],
52
53 ['l1DMode',{desc:"L1D Cache",
54 map : [["0k",0x0000],
55 ["4k",0x1000],
56 ["8k",0x2000],
57 ["16k",0x4000],
58 ["32k",0x8000]],
59 defaultValue: "0k",
60 memorySection: "L1DSRAM"}],
61
62 ['l2Mode',{desc:"L2 Cache",
63 map : [["0k",0x0000],
64 ["32k",0x8000],
65 ["64k",0x10000]],
66 defaultValue: "0k",
67 memorySection: "IRAM"}],
68
69 ];
70
71 instance:
72
73 override config string cpuCore = "64x+";
74 override config string isa = "64P";
75 override config string cpuCoreRevision = "1.0";
76
77 override config int minProgUnitSize = 1;
78 override config int minDataUnitSize = 1;
79 override config int dataWordSize = 4;
80
81 /*!
82 * ======== memMap ========
83 * The default memory map for this device
84 */
85 config xdc.platform.IPlatform.Memory memMap[string] = [
86 ["IRAM", {
87 comment: "Internal 64KB UMAP0 memory",
88 name: "IRAM",
89 base: 0x11800000,
90 len: 0x00010000,
91 space: "code/data",
92 access: "RWX"
93 }],
94
95 ["L1PSRAM", {
96 comment: "Internal 32KB RAM/CACHE L1 program memory",
97 name: "L1PSRAM",
98 base: 0x11E08000,
99 len: 0x00008000,
100 space: "code",
101 access: "RWX"
102 }],
103
104 ["L1DSRAM", {
105 comment: "Internal 80KB RAM/CACHE L1 data memory",
106 name: "L1DSRAM",
107 base: 0x11F04000,
108 len: 0x00014000,
109 space: "data",
110 access: "RW"
111 }],
112
113 ["ARM_RAM", {
114 comment: "Internal ARM RAM memory",
115 name: "ARM_RAM",
116 base: 0x10008000,
117 len: 0x00004000,
118 space: "data",
119 access: "RW"
120 }],
121 ];
122 };
123 /*
124 * @(#) ti.catalog.c6000; 1, 0, 0, 0,276; 8-7-2010 18:18:08; /db/ztree/library/trees/platform/platform-l20x/src/
125 */
126