1 import ti.catalog.msp430.peripherals.clock.IClock;
2 import ti.catalog.msp430.peripherals.special_function.IE1;
3
4 /*!
5 * ======== WDT+ ========
6 * MSP430 Watchdog Timer+
7 */
8 metaonly module WDTPlus inherits xdc.platform.IPeripheral {
9
10 enum WDTPW_t {
11 WDTPW_OFF = 0x00,
12 WDTPW = 0x5A00
13 };
14
15 enum WDTHOLD_t {
16 WDTHOLD_OFF = 0x0000,
17 WDTHOLD = (0x0080)
18 };
19
20 enum WDTNMIES_t {
21 WDTNMIES_OFF = (0x0000),
22 WDTNMIES = (0x0040)
23 };
24
25 enum WDTNMI_t {
26 WDTNMI_OFF = (0x0000),
27 WDTNMI = (0x0020)
28 };
29
30 enum WDTTMSEL_t {
31 WDTTMSEL_OFF = (0x0000),
32 WDTTMSEL = (0x0010)
33 };
34
35 enum WDTCNTCL_t {
36 WDTCNTCL_OFF = (0x0000),
37 WDTCNTCL = (0x0008)
38 };
39
40 enum WDTSSEL_t {
41 WDTSSEL_OFF = (0x0000),
42 WDTSSEL = (0x0004)
43 };
44
45 enum WDTIS1_t {
46 WDTIS1_OFF = (0x0000),
47 WDTIS1 = (0x0002)
48 };
49
50 enum WDTIS0_t {
51 WDTIS0_OFF = (0x0000),
52 WDTIS0 = (0x0001)
53 };
54
55
56 struct WDTCTL_t {
57 WDTPW_t WDTPW; /*! WDT+ password */
58 WDTHOLD_t WDTHOLD; /*! Watchdog timer+ hold. This bit stops the watchdog timer+. Setting
59 *WDTHOLD = 1 when the WDT+ is not in use conserves power.
60 * 0 Watchdog timer+ is not stopped
61 * 1 Watchdog timer+ is stopped
62 */
63 WDTNMIES_t WDTNMIES; /*! Watchdog timer+ NMI edge select. This bit selects the interrupt edge for the
64 *NMI interrupt when WDTNMI = 1. Modifying this bit can trigger an NMI. Modify
65 *this bit when WDTIE = 0 to avoid triggering an accidental NMI.
66 * 0 NMI on rising edge
67 * 1 NMI on falling edge
68 */
69 WDTNMI_t WDTNMI; /*! Watchdog timer+ NMI select. This bit selects the function for the RST/NMI pin.
70 * 0 Reset function
71 * 1 NMI function
72 */
73 WDTTMSEL_t WDTTMSEL; /*! Watchdog timer+ mode select
74 * 0 Watchdog mode
75 * 1 Interval timer mode
76 */
77 WDTCNTCL_t WDTCNTCL; /*! Watchdog timer+ counter clear. Setting WDTCNTCL = 1 clears the count
78 *value to 0000h. WDTCNTCL is automatically reset.
79 * 0 No action
80 * 1 WDTCNT = 0000h
81 */
82 WDTSSEL_t WDTSSEL; /*! Watchdog timer+ clock source select
83 * 0 SMCLK
84 * 1 ACLK
85 */
86 WDTIS0_t WDTIS0; /*! Watchdog timer+ interval select. These bits select the watchdog timer+
87 *interval to set the WDTIFG flag and/or generate a PUC.
88 * 00 Watchdog clock source /32768
89 * 01 Watchdog clock source /8192
90 * 10 Watchdog clock source /512
91 * 11 Watchdog clock source /64
92 */
93 WDTIS1_t WDTIS1; /*! Watchdog timer+ interval select. These bits select the watchdog timer+
94 *interval to set the WDTIFG flag and/or generate a PUC.
95 * 00 Watchdog clock source /32768
96 * 01 Watchdog clock source /8192
97 * 10 Watchdog clock source /512
98 * 11 Watchdog clock source /64
99 */
100 }
101
102 create(IClock.Instance clock , IE1.Instance interruptEnableRegister1);
103
104 instance:
105 /*! WDTCTL, Watchdog Timer+ Register */
106 config WDTCTL_t WDTCTL = {
107 WDTPW : WDTPW,
108 WDTHOLD : WDTHOLD_OFF,
109 WDTNMIES : WDTNMIES_OFF,
110 WDTNMI : WDTNMI_OFF,
111 WDTTMSEL : WDTTMSEL_OFF,
112 WDTCNTCL : WDTCNTCL_OFF,
113 WDTSSEL : WDTSSEL_OFF,
114 WDTIS0 : WDTIS0_OFF,
115 WDTIS1 : WDTIS1_OFF,
116 };
117
118 /*! @_nodoc */
119 config IClock.Instance clock;
120
121 /*! @_nodoc */
122 config IE1.Instance interruptEnableRegister1;
123 }