1 import ti.catalog.msp430.peripherals.clock.IClock;
2
3 /*!
4 * ======== ITimer_A ========
5 * MSP430 ITimer_A interface
6 */
7 metaonly interface ITimer_A inherits xdc.platform.IPeripheral {
8
9 enum TASSEL_t {
10 TASSEL_0 = (0*0x100u), /*! TACLK */
11 TASSEL_1 = (1*0x100u), /*! ACLK */
12 TASSEL_2 = (2*0x100u), /*! SMCLK */
13 TASSEL_3 = 3*0x100u /*! INCLK */
14 };
15
16 enum TACLR_t {
17 TACLR_OFF = (0x0000),
18 TACLR = 0x0004
19 };
20
21 enum TAIE_t {
22 TAIE_OFF = (0x0000),
23 TAIE = 0x0002
24 };
25
26 enum TAIFG_t {
27 TAIFG_OFF = (0x000),
28 TAIFG = (0x0001)
29 };
30
31 enum MC_t {
32 MC_0 = (0*0x10u), /*! Stop Mode */
33 MC_1 = (1*0x10u), /*! Up Mode */
34 MC_2 = (2*0x10u), /*! Continuous Mode */
35 MC_3 = 3*0x10u /*! Up/Down Mode */
36 };
37
38 enum ID_t {
39 ID_0 = (0*0x40u), /*! Divider - /1 */
40 ID_1 = (1*0x40u), /*! Divider - /2 */
41 ID_2 = (2*0x40u), /*! Divider - /4 */
42 ID_3 = 3*0x40u /*! Divider - /8 */
43 };
44
45 enum CM_t {
46 CM_0 = (0*0x4000u), /*! No Capture */
47 CM_1 = (1*0x4000u), /*! Rising Edge */
48 CM_2 = (2*0x4000u), /*! Falling Edge */
49 CM_3 = 3*0x4000u /*! Both Edges */
50 };
51
52 enum CCIS_t {
53 CCIS_0 = (0*0x1000u), /*! CCIxA */
54 CCIS_1 = (1*0x1000u), /*! CCIxB */
55 CCIS_2 = (2*0x1000u), /*! GND */
56 CCIS_3 = 3*0x1000u /*! Vcc */
57 };
58
59 enum SCS_t {
60 SCS_OFF = (0x0000), /*! Asynchronous Capture */
61 SCS = 0x0800 /*! Sychronous Capture */
62 };
63
64 enum SCCI_t {
65 SCCI_OFF = (0x0000), /*! Latched capture signal (read) */
66 SCCI = 0x0400 /*! Latched capture signal (read) */
67 };
68
69 enum CAP_t {
70 CAP_OFF = (0x0000), /*! Compare mode */
71 CAP = 0x0100 /*! Capture mode */
72 };
73
74 enum CCIE_t {
75 CCIE_OFF = (0x0000),
76 CCIE = (0x0010)
77 };
78
79 enum CCI_t {
80 CCI_OFF = (0x0008),
81 CCI = (0x0008)
82 };
83
84 enum OUT_t {
85 OUT_OFF = (0x0000),
86 OUT = (0x0004)
87 };
88
89 enum COV_t {
90 COV_OFF = (0x0000),
91 COV = (0x0002)
92 };
93
94 enum CCIFG_t {
95 CCIFG_OFF = (0x0000),
96 CCIFG = (0x0001)
97 };
98
99 enum OUTMOD_t {
100 OUTMOD_0 = (0*0x20u), /*! PWM output mode: 0 - OUT bit value */
101 OUTMOD_1 = (1*0x20u), /*! PWM output mode: 1 - Set */
102 OUTMOD_2 = (2*0x20u), /*! PWM output mode: 2 - PWM toggle/reset */
103 OUTMOD_3 = (3*0x20u), /*! PWM output mode: 3 - PWM set/reset */
104 OUTMOD_4 = (4*0x20u), /*! PWM output mode: 4 - Toggle */
105 OUTMOD_5 = (5*0x20u), /*! PWM output mode: 5 - Reset */
106 OUTMOD_6 = (6*0x20u), /*! PWM output mode: 6 - PWM toggle/set */
107 OUTMOD_7 = 7*0x20u /*! PWM output mode: 7 - PWM reset/set */
108 };
109
110 /*! TA3IV Definitions */
111 enum IVValues {
112 TAIV_NONE = 0x0000, /*! No Interrupt pending */
113 TAIV_TACCR1 = 0x0002, /*! TACCR1_CCIFG */
114 TAIV_TACCR2 = 0x0004, /*! TACCR2_CCIFG */
115 TAIV_6 = 0x0006, /*! Reserved */
116 TAIV_8 = 0x0008, /*! Reserved */
117 TAIV_TAIFG = 0x000A /*! TAIFG */
118 };
119
120 /*!
121 * ======== TACTL_t ========
122 * Timer_A Control Register
123 *
124 * @see #TACTL_t
125 */
126 struct TACTL_t {
127 TASSEL_t TASSEL; /*! Timer_A clock source select
128 * 00 TACLK
129 * 01 ACLK
130 * 10 SMCLK
131 * 11 INCLK */
132 ID_t ID; /*! Input divider. These bits select the divider for the input clock.
133 * 00 /1
134 * 01 /2
135 * 10 /4
136 * 11 /8 */
137 MC_t MC; /*! Mode control. Setting MCx = 00h when Timer_A is not in use conserves
138 * power.
139 * 00 Stop mode: the timer is halted.
140 * 01 Up mode: the timer counts up to TACCR0.
141 * 10 Continuous mode: the timer counts up to 0FFFFh.
142 * 11 Up/down mode: the timer counts up to TACCR0 then down to 0000h. */
143 TACLR_t TACLR; /*! Timer_A clear. Setting this bit resets TAR, the clock divider, and the count
144 * direction. The TACLR bit is automatically reset and is always read as zero. */
145 TAIE_t TAIE; /*! Timer_A interrupt enable. This bit enables the TAIFG interrupt request.
146 * 0 Interrupt disabled
147 * 1 Interrupt enabled */
148 TAIFG_t TAIFG; /*! Timer_A interrupt flag
149 * 0 No interrupt pending
150 * 1 Interrupt pending */
151 }
152
153 /*!
154 * ======== TACCTLx_t ========
155 * Capture/Compare Control Register
156 *
157 * @see #TACCTLx_t
158 */
159 struct TACCTLx_t {
160 CM_t CM; /*! Capture mode
161 * 00 No capture
162 * 01 Capture on rising edge
163 * 10 Capture on falling edge
164 * 11 Capture on both rising and falling edges */
165 CCIS_t CCIS; /*! Capture/compare input select. These bits select the TACCRx input signal.
166 * See the device-specific data sheet for specific signal connections.
167 * 00 CCIxA
168 * 01 CCIxB
169 * 10 GND
170 * 11 VCC */
171 SCS_t SCS; /*! Synchronize capture source. This bit is used to synchronize the capture input
172 * signal with the timer clock.
173 * 0 Asynchronous capture
174 * 1 Synchronous capture */
175 SCCI_t SCCI; /*! Synchronized capture/compare input. The selected CCI input signal is
176 * latched with the EQUx signal and can be read via this bit */
177 CAP_t CAP; /*! Capture mode
178 * 0 Compare mode
179 * 1 Capture mode */
180 OUTMOD_t OUTMOD; /*! Output mode. Modes 2, 3, 6, and 7 are not useful for TACCR0 because
181 * EQUx = EQU0.
182 * 000 OUT bit value
183 * 001 Set
184 * 010 Toggle/reset
185 * 011 Set/reset
186 * 100 Toggle
187 * 101 Reset
188 * 110 Toggle/set
189 * 111 Reset/set */
190 CCIE_t CCIE; /*! Capture/compare interrupt enable. This bit enables the interrupt request of
191 * the corresponding CCIFG flag.
192 * 0 Interrupt disabled
193 * 1 Interrupt enabled */
194 CCI_t CCI; /*! Capture/compare input. The selected input signal can be read by this bit. */
195 OUT_t OUT; /*! Output. For output mode 0, this bit directly controls the state of the output.
196 * 0 Output low
197 * 1 Output high */
198 COV_t COV; /*! Capture overflow. This bit indicates a capture overflow occurred. COV must
199 * be reset with software.
200 * 0 No capture overflow occurred
201 * 1 Capture overflow occurred */
202 CCIFG_t CCIFG; /*! Capture/compare interrupt flag
203 * 0 No interrupt pending
204 * 1 Interrupt pending */
205 }
206
207 create(IClock.Instance clock);
208
209 instance:
210 /*!
211 * ======== baseAddr ========
212 * Address of the peripheral's control register.
213 *
214 * A peripheral's registers are commonly accessed through a structure
215 * that defines the offsets of a particular register from the lowest
216 * address mapped to a peripheral. That lowest address is specified by
217 * this parameter.
218 */
219 config UInt baseAddr;
220
221 /*!
222 * ======== intNum ========
223 * Interrupt source number
224 *
225 */
226 config UInt intNum;
227
228 /*! Timer_A TACLK */
229 config float TACLK = 0;
230
231 /*! Timer_A INCLK */
232 config float INCLK = 0;
233
234 /*! @_nodoc */
235 config IClock.Instance clock;
236
237
238 UChar getNumberOfTimers();
239
240
241 float getTimer_A_OUT0();
242
243
244 float getTimer_A_OUT1();
245
246
247 float getTimer_A_OUT2();
248 }