1 import ti.catalog.msp430.peripherals.clock.IClock;
2
3 /*!
4 * ======== IFlash ========
5 * MSP430 IFlash interface
6 */
7 metaonly interface IFlash inherits xdc.platform.IPeripheral {
8
9 enum FWKEY_t {
10 FWKEY_OFF = 0x00,
11 FWKEY = 0xA500
12 };
13
14 /*! Block write mode */
15 enum BLKWRT_t {
16 BLKWRT_OFF = (0x0000), /* Block-write mode is off */
17 BLKWRT = (0x0080) /* Block-write mode is on */
18 };
19
20 /*! Write */
21 enum WRT_t {
22 WRT_OFF = (0x0000), /* Write mode is off */
23 WRT = 0x0040 /* Write mode is on */
24 };
25
26 /*! Enable Emergency Interrupt Exit */
27 enum EEIEX_t {
28 EEIEX_OFF = (0x0000), /* Exit interrupt disabled */
29 EEIEX = 0x0010 /* Exit interrupt enabled */
30 };
31
32 /*! Enable Erase Interrupts */
33 enum EEI_t {
34 EEI_OFF = (0x0000), /* Interrupts during segment erase disabled */
35 EEI = 0x0008 /* Interrupts during segment erase enabled */
36 };
37
38 /*! Mass erase */
39 enum MERAS_t {
40 MERAS_OFF = (0x0000), /* Mass erase disabled */
41 MERAS = 0x0004 /* Mass erase enabled */
42 };
43
44 /*! Erase */
45 enum ERASE_t {
46 ERASE_OFF = (0x0000), /* Erase disabled */
47 ERASE = 0x0002 /* Erase enabled */
48 };
49
50 enum FSSEL_t {
51 FSSEL_0 = 0x0000, /*! ACLK */
52 FSSEL_1 = 0x0040, /*! MCLK */
53 FSSEL_2 = 0x0080, /*! SMCLK */
54 FSSEL_3 = 0x00C0 /*! SMCLK */
55 };
56
57 /*! Flash controller clock divider bit 0 */
58 enum FN0_t {
59 FN0_OFF = (0x0000), /* Flash controller clock divider bit 0 */
60 FN0 = 0x0001 /* Flash controller clock divider bit 0 */
61 };
62
63 /*! Flash controller clock divider bit 1 */
64 enum FN1_t {
65 FN1_OFF = (0x0000), /* Flash controller clock divider bit 1 */
66 FN1 = 0x0002 /* Flash controller clock divider bit 1 */
67 };
68
69 /*! Flash controller clock divider bit 2 */
70 enum FN2_t {
71 FN2_OFF = (0x0000), /* Flash controller clock divider bit 2 */
72 FN2 = 0x0004 /* Flash controller clock divider bit 2 */
73 };
74
75 /*! Flash controller clock divider bit 3 */
76 enum FN3_t {
77 FN3_OFF = (0x0000), /* Flash controller clock divider bit 3 */
78 FN3 = 0x0008 /* Flash controller clock divider bit 3 */
79 };
80
81 /*! Flash controller clock divider bit 4 */
82 enum FN4_t {
83 FN4_OFF = (0x0000), /* Flash controller clock divider bit 4 */
84 FN4 = 0x0010 /* Flash controller clock divider bit 4 */
85 };
86
87 /*! Flash controller clock divider bit 5 */
88 enum FN5_t {
89 FN5_OFF = (0x0000), /* Flash controller clock divider bit 5 */
90 FN5 = 0x0020 /* Flash controller clock divider bit 5 */
91 };
92
93 /*! Operation failure */
94 enum FAIL_t {
95 FAIL_OFF = (0x0000), /* No failure */
96 FAIL = 0x0080 /* Failure */
97 };
98
99 /*! SegmentA and Info lock */
100 enum LOCKA_t {
101 LOCKA_OFF = (0x0000), /* Segment A unlocked and all information memory is erased during a mass erase */
102 LOCKA = 0x0040 /* Segment A locked and all information memory is protected from erasure during a mass erase */
103 };
104
105 /*! Emergency exit */
106 enum EMEX_t {
107 EMEX_OFF = (0x0000), /* No emergency exit */
108 EMEX = 0x0020 /* Emergency exit */
109 };
110
111 /*! Lock */
112 enum LOCK_t {
113 LOCK_OFF = (0x0000), /* Unlocked */
114 LOCK = 0x0010 /* Locked */
115 };
116
117 /*! Wait */
118 enum WAIT_t {
119 WAIT_OFF = (0x0000), /* The flash memory is not ready for the next byte/word write */
120 WAIT = 0x0008 /* The flash memory is ready for the next byte/word write */
121 };
122
123 /*! Access violation interrupt flag */
124 enum ACCVIFG_t {
125 ACCVIFG_OFF = (0x0000), /* No interrupt pending */
126 ACCVIFG = 0x0004 /* Interrupt pending */
127 };
128
129 /*! Flash security key violation */
130 enum KEYV_t {
131 KEYV_OFF = (0x0000), /* FCTLx password was written correctly */
132 KEYV = 0x0002 /* FCTLx password was written incorrectly */
133 };
134
135 /*! Busy */
136 enum BUSY_t {
137 BUSY_OFF = (0x0000), /* Not Busy */
138 BUSY = 0x0001 /* Busy */
139 };
140
141 create(IClock.Instance clock);
142
143 instance:
144 /*!
145 * ======== baseAddr ========
146 * Address of the peripheral's control register.
147 *
148 * A peripheral's registers are commonly accessed through a structure
149 * that defines the offsets of a particular register from the lowest
150 * address mapped to a peripheral. That lowest address is specified by
151 * this parameter.
152 */
153 config UInt baseAddr;
154
155 /*!
156 * ======== intNum ========
157 * Interrupt source number
158 *
159 */
160 config UInt intNum;
161
162 /*! @_nodoc */
163 config IClock.Instance clock;
164 }