1 /*!
2 * Universal Serial Communication Interface
3 */
4 metaonly interface IUSCI_UART inherits IUSCI {
5
6
7
8
9
10 /*! Parity enable */
11 enum UCPEN_t {
12 UCPEN_OFF = 0x00, /*! Parity Disabled */
13 UCPEN = 0x02 /*! Parity Enabled */
14 };
15
16 /*! Parity select. UCPAR is not used when parity is disabled. */
17 enum UCPAR_t {
18 UCPAR_OFF = 0x00, /*! Odd parity */
19 UCPAR = 0x02 /*! Even parity */
20 };
21
22 /*! Stop bit select. Number of stop bits. */
23 enum UCSPB_t {
24 UCSPB_OFF = 0x00, /*! One stop bit */
25 UCSPB = 0x02 /*! Two stop bits */
26 };
27
28 /*! First modulation stage select */
29 enum UCBRF_t {
30 UCBRF_0 = 0x00, /*! First stage 0 */
31 UCBRF_1 = 0x10, /*! First stage 1 */
32 UCBRF_2 = 0x20, /*! First stage 2 */
33 UCBRF_3 = 0x30, /*! First stage 3 */
34 UCBRF_4 = 0x40, /*! First stage 4 */
35 UCBRF_5 = 0x50, /*! First stage 5 */
36 UCBRF_6 = 0x60, /*! First stage 6 */
37 UCBRF_7 = 0x70, /*! First stage 7 */
38 UCBRF_8 = 0x80, /*! First stage 8 */
39 UCBRF_9 = 0x90, /*! First stage 9 */
40 UCBRF_10 = 0xA0, /*! First stage 10 */
41 UCBRF_11 = 0xB0, /*! First stage 11 */
42 UCBRF_12 = 0xC0, /*! First stage 12 */
43 UCBRF_13 = 0xD0, /*! First stage 13 */
44 UCBRF_14 = 0xE0, /*! First stage 14 */
45 UCBRF_15 = 0xF0 /*! First stage 15 */
46 };
47
48 /*! Second modulation stage select */
49 enum UCBRS_t {
50 UCBRS_0 = 0x00, /*! Second stage 0 */
51 UCBRS_1 = 0x02, /*! Second stage 1 */
52 UCBRS_2 = 0x04, /*! Second stage 2 */
53 UCBRS_3 = 0x06, /*! Second stage 3 */
54 UCBRS_4 = 0x08, /*! Second stage 4 */
55 UCBRS_5 = 0x0A, /*! Second stage 5 */
56 UCBRS_6 = 0x0C, /*! Second stage 6 */
57 UCBRS_7 = 0x0E /*! Second stage 7 */
58 };
59
60 /*! Oversampling mode enabled */
61 enum UCOS16_t {
62 UCOS16_OFF = 0x00, /*! Disabled. */
63 UCOS16 = 0x02 /*! Enabled. */
64 };
65
66
67 /*! IRDA Transmit Pulse Length Bit 5 */
68 enum UCIRTXPL5_t {
69 UCIRTXPL5_OFF = 0x00, /*! Bit 5 OFF */
70 UCIRTXPL5 = 0x80 /*! Bit 5 ON */
71 };
72
73 /*! IRDA Transmit Pulse Length Bit 4 */
74 enum UCIRTXPL4_t {
75 UCIRTXPL4_OFF = 0x00, /*! Bit 4 OFF */
76 UCIRTXPL4 = 0x40 /*! Bit 4 ON */
77 };
78
79 /*! IRDA Transmit Pulse Length Bit 3 */
80 enum UCIRTXPL3_t {
81 UCIRTXPL3_OFF = 0x00, /*! Bit 3 OFF */
82 UCIRTXPL3 = 0x20 /*! Bit 3 ON */
83 };
84
85 /*! IRDA Transmit Pulse Length Bit 2 */
86 enum UCIRTXPL2_t {
87 UCIRTXPL2_OFF = 0x00, /*! Bit 2 OFF */
88 UCIRTXPL2 = 0x10 /*! Bit 2 ON */
89 };
90
91 /*! IRDA Transmit Pulse Length Bit 1 */
92 enum UCIRTXPL1_t {
93 UCIRTXPL1_OFF = 0x00, /*! Bit 1 OFF */
94 UCIRTXPL1 = 0x08 /*! Bit 1 ON */
95 };
96
97 /*! IRDA Transmit Pulse Length Bit 0 */
98 enum UCIRTXPL0_t {
99 UCIRTXPL0_OFF = 0x00, /*! Bit 0 OFF */
100 UCIRTXPL0 = 0x04 /*! Bit 0 ON */
101 };
102
103 /*! IrDA transmit pulse clock select. */
104 enum UCIRTXCLK_t {
105 UCIRTXCLK_OFF = 0x00, /*! BRCLK. */
106 UCIRTXCLK = 0x02 /*! BITCLK16 when UCOS16 = 1. Otherwise, BRCLK. */
107 };
108
109 /*! IrDA encoder/decoder enable. */
110 enum UCIREN_t {
111 UCIREN_OFF = 0x00, /*! IrDA encoder/decoder disabled. */
112 UCIREN = 0x02 /*! IrDA encoder/decoder enabled. */
113 };
114
115 /*! IRDA Receive Filter Length Bit 5 */
116 enum UCIRRXFL5_t {
117 UCIRRXFL5_OFF = 0x00, /*! Bit 5 OFF */
118 UCIRRXFL5 = 0x80 /*! Bit 5 ON */
119 };
120
121 /*! IRDA Receive Filter Length Bit 4 */
122 enum UCIRRXFL4_t {
123 UCIRRXFL4_OFF = 0x00, /*! Bit 4 OFF */
124 UCIRRXFL4 = 0x40 /*! Bit 4 ON */
125 };
126
127 /*! IRDA Receive Filter Length Bit 3 */
128 enum UCIRRXFL3_t {
129 UCIRRXFL3_OFF = 0x00, /*! Bit 3 OFF */
130 UCIRRXFL3 = 0x20 /*! Bit 3 ON */
131 };
132
133 /*! IRDA Receive Filter Length Bit 2 */
134 enum UCIRRXFL2_t {
135 UCIRRXFL2_OFF = 0x00, /*! Bit 2 OFF */
136 UCIRRXFL2 = 0x10 /*! Bit 2 ON */
137 };
138
139 /*! IRDA Receive Filter Length Bit 1 */
140 enum UCIRRXFL1_t {
141 UCIRRXFL1_OFF = 0x00, /*! Bit 1 OFF */
142 UCIRRXFL1 = 0x08 /*! Bit 1 ON */
143 };
144
145 /*! IRDA Receive Filter Length Bit 0 */
146 enum UCIRRXFL0_t {
147 UCIRRXFL0_OFF = 0x00, /*! Bit 0 OFF */
148 UCIRRXFL0 = 0x04 /*! Bit 0 ON */
149 };
150
151 /*! IrDA receive input UCAxRXD polarity. */
152 enum UCIRRXPL_t {
153 UCIRRXPL_OFF = 0x00, /*! IrDA transceiver delivers a high pulse when a light pulse is seen. */
154 UCIRRXPL = 0x02 /*! IrDA transceiver delivers a low pulse when a light pulse is seen. */
155 };
156
157 /*! IrDA receive filter enabled. */
158 enum UCIRRXFE_t {
159 UCIRRXFE_OFF = 0x00, /*! Receive filter disabled. */
160 UCIRRXFE = 0x02 /*! Receive filter enabled. */
161 };
162
163 /*! Break/synch delimiter length bit 0 */
164 enum UCDELIM0_t {
165 UCDELIM0_OFF = 0x00, /*! Break Sync Delimiter bit 0 Off */
166 UCDELIM0 = 0x02 /*! Break Sync Delimiter bit 0 On */
167 };
168
169 /*! Break/synch delimiter length bit 1 */
170 enum UCDELIM1_t {
171 UCDELIM1_OFF = 0x00, /*! Break Sync Delimiter bit 1 Off */
172 UCDELIM1 = 0x02 /*! Break Sync Delimiter bit 1 On */
173 };
174
175 /*! Synch field time out error. */
176 enum UCSTOE_t {
177 UCSTOE_OFF = 0x00, /*! No error. */
178 UCSTOE = 0x02 /*! Length of synch field exceeded measurable time. */
179 };
180
181 /*! Break time out error. */
182 enum UCBTOE_t {
183 UCBTOE_OFF = 0x00, /*! No error. */
184 UCBTOE = 0x02 /*! Length of break field exceeded 22 bit times. */
185 };
186
187 /*! Automatic baud rate detect enable. */
188 enum UCABDEN_t {
189 UCABDEN_OFF = 0x00, /*! Baud rate detection disabled. Length of break and synch field is not
190 * measured. */
191 UCABDEN = 0x02 /*! Baud rate detection enabled. Length of break and synch field is
192 * measured and baud rate settings are changed accordingly. */
193 };
194
195 /*! USCI mode. The UCMODEx bits select the asynchronous mode when UCSYNC = 0. */
196 enum UCMODE_ASYNC_t {
197 UCMODE_0 = 0x00, /*! UART Mode. */
198 UCMODE_1 = 0x01, /*! Idle-Line Multiprocessor Mode. */
199 UCMODE_2 = 0x02, /*! Address-Bit Multiprocessor Mode. */
200 UCMODE_3 = 0x04 /*! UART Mode with automatic baud rate detection. */
201 };
202
203 /*! USCI clock source select. These bits select the BRCLK source clock. */
204 enum UCSSEL_UART_t {
205 UCSSEL_0 = 0x00, /*! UCLK */
206 UCSSEL_1 = 0x01, /*! ACLK */
207 UCSSEL_2 = 0x02 /*! SMCLK */
208
209 };
210
211 struct UCxCTL0_t {
212 UCPEN_t UCPEN; /*! Parity enable
213 * 0 Parity disabled.
214 * 1 Parity enabled. Parity bit is generated (UCAxTXD) and expected
215 * (UCAxRXD). In address-bit multiprocessor mode, the address bit is
216 * included in the parity calculation. */
217 UCPAR_t UCPAR; /*! Parity select. UCPAR is not used when parity is disabled.
218 * 0 Odd parity
219 * 1 Even parity */
220 UCMSB_t UCMSB; /*! MSB first select. Controls the direction of the receive and transmit shift
221 *register.
222 * 0 LSB first
223 * 1 MSB first */
224 UC7BIT_t UC7BIT; /*! Character length. Selects 7-bit or 8-bit character length.
225 * 0 8-bit data
226 * 1 7-bit data */
227 UCSPB_t UCSPB; /*! Stop bit select. Number of stop bits.
228 * 0 One stop bit
229 * 1 Two stop bits */
230 UCMODE_ASYNC_t UCMODE; /*! USCI mode. The UCMODEx bits select the asynchronous mode when
231 *UCSYNC = 0.
232 * 00 UART Mode.
233 * 01 Idle-Line Multiprocessor Mode.
234 * 10 Address-Bit Multiprocessor Mode.
235 * 11 UART Mode with automatic baud rate detection. */
236 UCSYNC_t UCSYNC; /*!Synchronous mode enable
237 * 0 Asynchronous mode
238 * 1 Synchronous Mode */
239 }
240
241 struct UCxCTL1_t {
242 UCSSEL_UART_t UCSSEL; /*! USCI clock source select. These bits select the BRCLK source clock.
243 * 00 UCLK
244 * 01 ACLK
245 * 10 SMCLK
246 * 11 SMCLK */
247 UCRXEIE_t UCRXEIE; /*! Receive erroneous-character interrupt-enable
248 * 0 Erroneous characters rejected and UCAxRXIFG is not set
249 * 1 Erroneous characters received will set UCAxRXIFG */
250 UCBRKIE_t UCBRKIE; /*! Receive break character interrupt-enable
251 * 0 Received break characters do not set UCAxRXIFG.
252 * 1 Received break characters set UCAxRXIFG. */
253 UCDORM_t UCDORM; /*! Dormant. Puts USCI into sleep mode.
254 * 0 Not dormant. All received characters will set UCAxRXIFG.
255 * 1 Dormant. Only characters that are preceded by an idle-line or with
256 * address bit set will set UCAxRXIFG. In UART mode with automatic baud
257 * rate detection only the combination of a break and synch field will set
258 * UCAxRXIFG. */
259 UCTXADDR_t UCTXADDR; /*! Transmit address. Next frame to be transmitted will be marked as address
260 *depending on the selected multiprocessor mode.
261 * 0 Next frame transmitted is data
262 * 1 Next frame transmitted is an address */
263 UCTXBRK_t UCTXBRK; /*! Transmit break. Transmits a break with the next write to the transmit buffer.
264 *In UART mode with automatic baud rate detection 055h must be written
265 *into UCAxTXBUF to generate the required break/synch fields. Otherwise
266 *0h must be written into the transmit buffer.
267 * 0 Next frame transmitted is not a break
268 * 1 Next frame transmitted is a break or a break/synch */
269 UCSWRST_t UCSWRST; /*! Software reset enable
270 * 0 Disabled. USCI reset released for operation.
271 * 1 Enabled. USCI logic held in reset state. */
272 }
273
274 struct UCxMCTL_t {
275 UCBRF_t UCBRF; /*! First modulation stage select. These bits determine the modulation pattern
276 *for BITCLK16 when UCOS16 = 1. Ignored with UCOS16 = 0. */
277 UCBRS_t UCBRS; /*! Second modulation stage select. These bits determine the modulation
278 *pattern for BITCLK. */
279 UCOS16_t UCOS16; /*! Oversampling mode enabled
280 * 0 Disabled
281 * 1 Enabled */
282 }
283
284 struct UCxSTAT_t {
285 UCLISTEN_t UCLISTEN; /*! Listen enable. The UCLISTEN bit selects loopback mode.
286 * 0 Disabled
287 * 1 Enabled. UCAxTXD is internally fed back to the receiver. */
288 UCFE_t UCFE; /*! Framing error flag
289 * 0 No error
290 * 1 Character received with low stop bit */
291 UCOE_t UCOE; /*! Overrun error flag. This bit is set when a character is transferred into
292 *UCAxRXBUF before the previous character was read. UCOE is cleared
293 *automatically when UCxRXBUF is read, and must not be cleared by
294 *software. Otherwise, it will not function correctly.
295 * 0 No error
296 * 1 Overrun error occurred */
297 UCPE_t UCPE; /*! Parity error flag. When UCPEN = 0, UCPE is read as 0.
298 * 0 No error
299 * 1 Character received with parity error */
300 UCBRK_t UCBRK; /*! Break detect flag
301 * 0 No break condition
302 * 1 Break condition occurred */
303 UCRXERR_t UCRXERR; /*! Receive error flag. This bit indicates a character was received with error(s).
304 *When UCRXERR = 1, on or more error flags (UCFE, UCPE, UCOE) is also
305 *set. UCRXERR is cleared when UCAxRXBUF is read.
306 * 0 No receive errors detected
307 * 1 Receive error detected */
308 UCADDR_t UCADDR; /*! Address received in address-bit multiprocessor mode.
309 * 0 Received character is data
310 * 1 Received character is an address */
311 UCIDLE_t UCIDLE; /*! Idle line detected in idle-line multiprocessor mode.
312 * 0 No idle line detected
313 * 1 Idle line detected */
314 UCBUSY_t UCBUSY; /*! USCI busy. This bit indicates if a transmit or receive operation is in
315 *progress.
316 * 0 USCI inactive
317 * 1 USCI transmitting or receiving */
318 }
319
320 struct UCxIRTCTL_t {
321 UCIRTXPL5_t UCIRTXPL5; /*! IRDA Transmit Pulse Length Bit 5 */
322 UCIRTXPL4_t UCIRTXPL4; /*! IRDA Transmit Pulse Length Bit 4 */
323 UCIRTXPL3_t UCIRTXPL3; /*! IRDA Transmit Pulse Length Bit 3 */
324 UCIRTXPL2_t UCIRTXPL2; /*! IRDA Transmit Pulse Length Bit 2 */
325 UCIRTXPL1_t UCIRTXPL1; /*! IRDA Transmit Pulse Length Bit 1 */
326 UCIRTXPL0_t UCIRTXPL0; /*! IRDA Transmit Pulse Length Bit 0 */
327 UCIRTXCLK_t UCIRTXCLK; /*! IrDA transmit pulse clock select
328 * 0 BRCLK
329 * 1 BITCLK16 when UCOS16 = 1. Otherwise, BRCLK */
330 UCIREN_t UCIREN; /*! IrDA encoder/decoder enable.
331 * 0 IrDA encoder/decoder disabled
332 * 1 IrDA encoder/decoder enabled */
333 }
334
335 struct UCxIRRCTL_t {
336 UCIRRXFL5_t UCIRRXFL5; /*! IRDA Receive Filter Length Bit 5 */
337 UCIRRXFL4_t UCIRRXFL4; /*! IRDA Receive Filter Length Bit 4 */
338 UCIRRXFL3_t UCIRRXFL3; /*! IRDA Receive Filter Length Bit 3 */
339 UCIRRXFL2_t UCIRRXFL2; /*! IRDA Receive Filter Length Bit 2 */
340 UCIRRXFL1_t UCIRRXFL1; /*! IRDA Receive Filter Length Bit 1 */
341 UCIRRXFL0_t UCIRRXFL0; /*! IRDA Receive Filter Length Bit 0 */
342 UCIRRXPL_t UCIRRXPL; /*! IrDA receive input UCAxRXD polarity
343 * 0 IrDA transceiver delivers a high pulse when a light pulse is seen
344 * 1 IrDA transceiver delivers a low pulse when a light pulse is seen */
345 UCIRRXFE_t UCIRRXFE; /*! IrDA receive filter enabled
346 * 0 Receive filter disabled
347 * 1 Receive filter enabled */
348 }
349
350 struct UCxABCTL_t {
351 UCDELIM1_t UCDELIM1; /*! Break/synch delimiter length
352 * 00 1 bit time
353 * 01 2 bit times
354 * 10 3 bit times
355 * 11 4 bit times */
356 UCDELIM0_t UCDELIM0; /*! Break/synch delimiter length
357 * 00 1 bit time
358 * 01 2 bit times
359 * 10 3 bit times
360 * 11 4 bit times */
361 UCSTOE_t UCSTOE; /*! Synch field time out error
362 * 0 No error
363 * 1 Length of synch field exceeded measurable time */
364 UCBTOE_t UCBTOE; /*! Break time out error
365 * 0 No error
366 * 1 Length of break field exceeded 22 bit times */
367 UCABDEN_t UCABDEN; /*! Automatic baud rate detect enable
368 * 0 Baud rate detection disabled. Length of break and synch field is not
369 * measured.
370 * 1 Baud rate detection enabled. Length of break and synch field is
371 * measured and baud rate settings are changed accordingly. */
372 }
373 }