1 /*!
2 * Universal Serial Communication Interface
3 */
4 metaonlyinterface IUSCI_SPI inherits IUSCI {
5
6 //*****************************************************************
7 //* REGISTER BIT DEFINITIONS *
8 //*****************************************************************
9
10 /*! Clock phase select. */
11 enum UCCKPH_t {
12 UCCKPH_OFF = 0x00, /*! Data is changed on the first UCLK edge and captured on the following edge. */
13 UCCKPH = 0x80 /*! Data is captured on the first UCLK edge and changed on the following edge. */
14 };
15
16 /*! Clock polarity select. */
17 enum UCCKPL_t {
18 UCCKPL_OFF = 0x00, /*! Inactive state is low */
19 UCCKPL = 0x40 /*! Inactive state is high */
20 };
21
22 /*! Master mode select */
23 enum UCMST_t {
24 UCMST_OFF = 0x00, /*! Slave mode */
25 UCMST = 0x40 /*! Master mode */
26 };
27
28 /*! USCI clock source select. These bits select the BRCLK source clock. */
29 enum UCSSEL_SPI_t {
30 UCSSEL_0 = 0x00, /*! NA */
31 UCSSEL_1 = 0x01, /*! ACLK */
32 UCSSEL_2 = 0x02 /*! SMCLK */
33 /* UCSSEL_3 = 0x04 /*! SMCLK */
34 };
35
36 struct UCxCTL0_t {
37 UCCKPH_t UCCKPH; /*! Clock phase select.
38 * 0 Data is changed on the first UCLK edge and captured on the
39 * following edge.
40 * 1 Data is captured on the first UCLK edge and changed on the
41 * following edge. */
42 UCCKPL_t UCCKPL; /*! Clock polarity select.
43 * 0 The inactive state is low.
44 * 1 The inactive state is high. */
45 UCMSB_t UCMSB; /*! MSB first select. Controls the direction of the receive and transmit shift
46 *register.
47 * 0 LSB first
48 * 1 MSB first */
49 UC7BIT_t UC7BIT; /*! Character length. Selects 7-bit or 8-bit character length.
50 * 0 8-bit data
51 * 1 7-bit data */
52 UCMST_t UCMST; /*! Master mode select
53 * 0 Slave mode
54 * 1 Master mode */
55 UCMODE_SYNC_t UCMODE; /*! USCI mode. The UCMODEx bits select the synchronous mode when
56 *UCSYNC = 1.
57 * 00 3-Pin SPI
58 * 01 4-Pin SPI with UCxSTE active high: slave enabled when UCxSTE = 1
59 * 10 4-Pin SPI with UCxSTE active low: slave enabled when UCxSTE = 0
60 * 11 I2C Mode */
61 UCSYNC_t UCSYNC; /*! Synchronous mode enable
62 * 0 Asynchronous mode
63 * 1 Synchronous Mode */
64 }
65
66 struct UCxCTL1_t {
67 UCSSEL_SPI_t UCSSEL; /*! USCI clock source select. These bits select the BRCLK source clock in
68 *master mode. UCxCLK is always used in slave mode.
69 * 00 NA
70 * 01 ACLK
71 * 10 SMCLK
72 * 11 SMCLK */
73 UCSWRST_t UCSWRST; /*! Software reset enable
74 * 0 Disabled. USCI reset released for operation.
75 * 1 Enabled. USCI logic held in reset state. */
76 }
77
78 struct UCxSTAT_t {
79 UCLISTEN_t UCLISTEN; /*! Listen enable. The UCLISTEN bit selects loopback mode.
80 * 0 Disabled
81 * 1 Enabled. UCAxTXD is internally fed back to the receiver. */
82 UCFE_t UCFE; /*! Framing error flag. This bit indicates a bus conflict in 4-wire master mode.
83 *UCFE is not used in 3-wire master or any slave mode.
84 * 0 No error
85 * 1 Bus conflict occurred */
86 UCOE_t UCOE; /*! Overrun error flag. This bit is set when a character is transferred into
87 *UCAxRXBUF before the previous character was read. UCOE is cleared
88 *automatically when UCxRXBUF is read, and must not be cleared by
89 *software. Otherwise, it will not function correctly.
90 * 0 No error
91 * 1 Overrun error occurred */
92 UCBUSY_t UCBUSY; /*! USCI busy. This bit indicates if a transmit or receive operation is in
93 *progress.
94 * 0 USCI inactive
95 * 1 USCI transmitting or receiving */
96 }
97 }