1 import ti.catalog.msp430.peripherals.special_function.IE1;
2
3 /*!
4 * ======== Clock ========
5 * MSP430 Master Clock
6 */
7 metaonly module Clock2xx inherits IClock {
8
9 /*! MOD0 Bit */
10 enum MOD0_t {
11 MOD0_OFF = 0x00, /*! Disable MOD0 bit */
12 MOD0 = 0x01 /*! Enable MOD0 bit */
13 };
14
15 /*! MOD1 Bit */
16 enum MOD1_t {
17 MOD1_OFF = 0x00, /*! Disable MOD1 bit */
18 MOD1 = 0x02 /*! Enable MOD1 bit */
19 };
20
21 /*! MOD2 Bit */
22 enum MOD2_t {
23 MOD2_OFF = 0x00, /*! Disable MOD2 bit */
24 MOD2 = 0x04 /*! Enable MOD2 bit */
25 };
26
27 /*! MOD3 Bit */
28 enum MOD3_t {
29 MOD3_OFF = 0x00, /*! Disable MOD3 bit */
30 MOD3 = 0x08 /*! Enable MOD3 bit */
31 };
32
33 /*! MOD4 Bit */
34 enum MOD4_t {
35 MOD4_OFF = 0x00, /*! Disable MOD4 bit */
36 MOD4 = 0x10 /*! Enable MOD4 bit */
37 };
38
39 /*! DCO0 Bit */
40 enum DCO0_t {
41 DCO0_OFF = 0x00, /*! Disable DCO0 bit */
42 DCO0 = 0x20 /*! Enable DCO0 bit */
43 };
44
45 /*! DCO1 Bit */
46 enum DCO1_t {
47 DCO1_OFF = 0x00, /*! Disable DCO1 bit */
48 DCO1 = 0x40 /*! Enable DCO1 bit */
49 };
50
51 /*! DCO2 Bit */
52 enum DCO2_t {
53 DCO2_OFF = 0x00, /*! Disable DCO2 bit */
54 DCO2 = 0x80 /*! Enable DCO2 bit */
55 };
56
57 enum XT2OFF_t {
58 XT2OFF_OFF = 0x00, /*! Enable XT2CLK */
59 XT2OFF = 0x80 /*! Disable XT2CLK */
60 };
61
62 enum XTS_t {
63 XTS_OFF = 0x00, /*! Low Frequency */
64 XTS = 0x40 /*! High Frequency */
65 };
66
67 enum RSEL0_t {
68 RSEL0_OFF = 0x00, /*! Disable RSEL0 bit */
69 RSEL0 = 0x80 /*! Enable RSEL0 bit */
70 };
71
72 enum RSEL1_t {
73 RSEL1_OFF = 0x00, /*! Disable RSEL1 bit */
74 RSEL1 = 0x80 /*! Enable RSEL1 bit */
75 };
76
77 enum RSEL2_t {
78 RSEL2_OFF = 0x00, /*! Disable RSEL2 bit */
79 RSEL2 = 0x80 /*! Enable RSEL2 bit */
80 };
81
82 enum RSEL3_t {
83 RSEL3_OFF = 0x00, /*! Disable RSEL3 bit */
84 RSEL3 = 0x80 /*! Enable RSEL3 bit */
85 };
86
87 /*! MCLK Source Select */
88 enum SELM_t {
89 SELM_0 = 0x00, /*! DCOCLK */
90
91 SELM_2 = 0x80, /*! XT2CLK/LFXTCLK */
92 SELM_3 = 0xC0 /*! LFXTCLK */
93 };
94
95 /*! ACLK Divider values */
96 enum DIVA_t {
97 DIVA_0 = 0x00, /*! Divide by 1 */
98 DIVA_1 = 0x10, /*! Divide by 2 */
99 DIVA_2 = 0x20, /*! Divide by 4 */
100 DIVA_3 = 0x30 /*! Divide by 8 */
101 };
102
103 /*! MCLK Divider values */
104 enum DIVM_t {
105 DIVM_0 = 0x00, /*! Divide by 1 */
106 DIVM_1 = 0x10, /*! Divide by 2 */
107 DIVM_2 = 0x20, /*! Divide by 4 */
108 DIVM_3 = 0x30 /*! Divide by 8 */
109 };
110
111 /*! SMCLK Divider values */
112 enum DIVS_t {
113 DIVS_0 = 0x00, /*! Divide by 1 */
114 DIVS_1 = 0x02, /*! Divide by 2 */
115 DIVS_2 = 0x04, /*! Divide by 4 */
116 DIVS_3 = 0x06 /*! Divide by 8 */
117 };
118
119 enum SELS_t {
120 SELS_OFF = 0x00, /*! DCOCLK */
121 SELS = 0x40 /*! XT2CLK */
122 };
123
124 enum DCOR_t {
125 DCOR_OFF = 0x00, /*! DCO uses internal resistor */
126 DCOR = 0x40 /*! DCO uses external resistor */
127 };
128
129 /*! XT2 frequency range select */
130 enum XT2S_t {
131 XT2S_0 = 0x00, /*! 0.4 - 1 MHz */
132 XT2S_1 = 0x40, /*! 1 - 3 MHz */
133 XT2S_2 = 0x80, /*! 3 - 16 MHz */
134 XT2S_3 = 0xC0 /*! Digital input signal */
135 };
136
137 enum LFXT1S_t {
138 LFXT1S_0 = 0x00, /*! XTS = 0, 32768kHz Crystal ; XTS = 1, 0.4 - 1-MHz crystal or resonator */
139 LFXT1S_1 = 0x10, /*! XTS = 0, Reserved ; XTS = 1, 1 - 3-MHz crystal or resonator */
140 LFXT1S_2 = 0x20, /*! XTS = 0, VLOCLK ; XTS = 1, 3 - 16-MHz crystal or resonator */
141 LFXT1S_3 = 0x30 /*! XTS = 0, Digital External ; XTS = 1, 0.4 - 16-MHz Digital External */
142 };
143
144 enum XCAP_t {
145 XCAP_0 = 0x00, /*! ~1 pF */
146 XCAP_1 = 0x04, /*! ~6 pF */
147 XCAP_2 = 0x08, /*! ~10 pF */
148 XCAP_3 = 0x0C /*! ~12.5 pF */
149 };
150
151 enum XT2OF_t {
152 XT2OF_OFF = 0x00, /*! No fault condition present */
153 XT2OF = 0x02 /*! XT2 fault condition present */
154 };
155
156 enum LFXT1OF_t {
157 LFXT1OF_OFF = 0x00, /*! No fault condition present */
158 LFXT1OF = 0x01 /*! LFXT1 fault condition present */
159 };
160
161 162 163
164 enum PreCalibratedValues_t {
165 PreCal_0, /*! 1 MHz */
166 PreCal_1, /*! 8 MHz */
167 PreCal_2, /*! 12 MHz */
168 PreCal_3, /*! 16 MHz */
169 PreCal_4 /*! Custom */
170 };
171
172 struct DCOCTL_t {
173 MOD0_t MOD0; /*! Modulation Bit 0 */
174 MOD1_t MOD1; /*! Modulation Bit 1 */
175 MOD2_t MOD2; /*! Modulation Bit 2 */
176 MOD3_t MOD3; /*! Modulation Bit 3 */
177 MOD4_t MOD4; /*! Modulation Bit 4 */
178 DCO0_t DCO0; /*! DCO Select Bit 0 */
179 DCO1_t DCO1; /*! DCO Select Bit 1 */
180 DCO2_t DCO2; /*! DCO Select Bit 2 */
181 }
182
183 /*!
184 * ======== BCSCTL1_t ========
185 * BCS Control Register 1
186 *
187 * @field(XT2OFF) This bit turns off the XT2 oscillator: 0 - XT2 is on,
188 * 1 - XT2 is off if it is not used for MCLK or SMCLK
189 *
190 * @field(XTS) 0 - Low frequency mode; 1 - High frequency mode
191 */
192 struct BCSCTL1_t {
193 XT2OFF_t XT2OFF; /*! XT2 off. This bit turns off the XT2 oscillator
194 * 0 XT2 is on
195 * 1 XT2 is off if it is not used for MCLK or SMCLK. */
196 XTS_t XTS; /*! LFXT1 mode select.
197 * 0 Low frequency mode
198 * 1 High frequency mode */
199 DIVA_t DIVA; /*! Divider for ACLK
200 * 00 /1
201 * 01 /2
202 * 10 /4
203 * 11 /8 */
204 RSEL0_t RSEL0; /*! Range select bit 0 */
205 RSEL1_t RSEL1; /*! Range select bit 1 */
206 RSEL2_t RSEL2; /*! Range select bit 2 */
207 RSEL3_t RSEL3; /*! Range select bit 3 */
208 }
209
210 /*!
211 * ======== BCSCTL2_t ========
212 * BCS Control Register 2
213 *
214 * @field(SELM) These bits select the MCLK source.
215 * @field(SELS) These bits select the SMCLK source. When
216 * XT2 oscillator present, 0 selects DCOCLK and
217 * 1 selects XT2CLK; otherwise 0 selects LFXT1CLK and
218 * 1 selects VLOCLK.
219 * @field(DCOR) 0 - Internal resistor, 1 - external resistor
220 */
221 struct BCSCTL2_t {
222 SELM_t SELM; /*! Select MCLK. These bits select the MCLK source.
223 * 00 DCOCLK
224 * 01 DCOCLK
225 * 10 XT2CLK when XT2 oscillator present on-chip. LFXT1CLK or VLOCLK
226 * when XT2 oscillator not present on-chip.
227 * 11 LFXT1CLK or VLOCLK */
228 DIVM_t DIVM; /*! Divider for MCLK
229 * 00 /1
230 * 01 /2
231 * 10 /4
232 * 11 /8 */
233 SELS_t SELS; /*! Select SMCLK. This bit selects the SMCLK source.
234 * 0 DCOCLK
235 * 1 XT2CLK when XT2 oscillator present. LFXT1CLK or VLOCLK when
236 * XT2 oscillator not present */
237 DIVS_t DIVS; /*! Divider for SMCLK
238 * 00 /1
239 * 01 /2
240 * 10 /4
241 * 11 /8 */
242 DCOR_t DCOR; /*! DCO resistor select
243 * 0 Internal resistor
244 * 1 External resistor */
245 }
246
247 /*!
248 * ======== BCSCTL3_t ========
249 * BCS Control register 3
250 *
251 * @field(LFXT1S) These bits select between LFXT1 and VLO and XTS = 0,
252 * and select the frequency range for LFXT1 when XTS = 1
253 * @field(XCAP) These bits select the effective capacitance seen by
254 * the LFXT1 crystal when XTS = 0. If XTS = 1 or if
255 * LFCT1Sx = 11, then XCAPx should be 00.
256 */
257 struct BCSCTL3_t {
258 XT2S_t XT2S; /*! XT2 range select. These bits select the frequency range for XT2.
259 * 00 0.4 - 1-MHz crystal or resonator
260 * 01 1 - 3-MHz crystal or resonator
261 * 10 3 - 16-MHz crystal or resonator
262 * 11 Digital external 0.4 - 16-MHz clock source */
263 LFXT1S_t LFXT1S; /*! Low-frequency clock select and LFXT1 range select. These bits select
264 * between LFXT1 and VLO when XTS = 0, and select the frequency range
265 * for LFXT1 when XTS = 1
266 *
267 * When XTS = 0:
268 * 00 32768 Hz Crystal on LFXT1
269 * 01 Reserved
270 * 10 VLOCLK (Reserved in MSP430x21x1 devices)
271 * 11 Digital external clock source
272 *
273 * When XTS = 1 (Not applicable for MSP430x20xx devices)
274 * 00 0.4 - 1-MHz crystal or resonator
275 * 01 1 - 3-MHz crystal or resonator
276 * 10 3 - 16-MHz crystal or resonator
277 * 11 Digital external 0.4 - 16-MHz clock source */
278 XCAP_t XCAP; /*! Oscillator capacitor selection. These bits select the effective capacitance
279 * seen by the LFXT1 crystal when XTS = 0. If XTS = 1 or if LFCT1Sx = 11
280 * XCAPx should be 00.
281 * 00 ~1 pF
282 * 01 ~6 pF
283 * 10 ~10 pF
284 * 11 ~12.5 pF */
285 XT2OF_t XT2OF; /*! XT2 oscillator fault
286 * 0 No fault condition present
287 * 1 Fault condition present */
288 LFXT1OF_t LFXT1OF; /*! LFXT1 oscillator fault
289 * 0 No fault condition present
290 * 1 Fault condition present */
291 }
292
293 create(IE1.Instance interruptEnableRegister1);
294
295 instance:
296
297 /*! DCO Clock Frequency Control */
298 config DCOCTL_t DCOCTL = {
299 MOD0 : MOD0_OFF,
300 MOD1 : MOD1_OFF,
301 MOD2 : MOD2_OFF,
302 MOD3 : MOD3_OFF,
303 MOD4 : MOD4_OFF,
304 DCO0 : DCO0,
305 DCO1 : DCO1,
306 DCO2 : DCO2_OFF,
307 };
308
309 /*! Basic Clock System Control 1 */
310 config BCSCTL1_t BCSCTL1 = {
311 XT2OFF : XT2OFF,
312 XTS : XTS_OFF,
313 DIVA : DIVA_0,
314 RSEL0 : RSEL0,
315 RSEL1 : RSEL1,
316 RSEL2 : RSEL2,
317 RSEL3 : RSEL3_OFF
318 };
319
320 /*! Basic Clock System Control 2 */
321 config BCSCTL2_t BCSCTL2 = {
322 SELM : SELM_0,
323 DIVM : DIVM_0,
324 SELS : SELS_OFF,
325 DIVS : DIVS_0,
326 DCOR : DCOR_OFF
327 };
328
329 /*! Basic Clock System Control 3 */
330 config BCSCTL3_t BCSCTL3 = {
331 XT2S : XT2S_0,
332 LFXT1S : LFXT1S_0,
333 XCAP : XCAP_1
334 };
335
336 /*! Basic Clock System 2xx pre-calibrated system frequency */
337 config PreCalibratedValues_t preCalibratedValues = PreCal_0;
338
339 config float VLOCLKHz = 12000;
340 config float WATCHCRYSTALCLKHz = 32768;
341 config float LFXT1CLKHz = 0;
342 config float XT2CLKHz = 0;
343
344 /*! Set whether XT2 is available on the device. */
345 config bool hasXT2 = false;
346
347 /*! @_nodoc */
348 config IE1.Instance interruptEnableRegister1;
349 }