1 import ti.catalog.msp430.peripherals.clock.IClock;
2 import ti.catalog.msp430.peripherals.timer.ITimer_A;
3
4 /*!
5 * ======== ADC10 ========
6 * MSP430 10-bit Analog to Digital Converter
7 */
8 metaonly module ADC10 inherits xdc.platform.IPeripheral {
9
10 /*! ADC10 Start Conversion */
11 enum ADC10SC_t {
12 ADC10SC_OFF = 0x000, /*! No conversion. */
13 ADC10SC = 0x001 /*! Start ADC conversion manually. */
14 };
15
16 /*! ADC10 Enable Conversion */
17 enum ENC_t {
18 ENC_OFF = 0x000, /*! Disable ADC. */
19 ENC = 0x002 /*! Enable ADC. */
20 };
21
22 /*! ADC10 Interrupt Flag */
23 enum ADC10IFG_t {
24 ADC10IFG_OFF = 0x000, /*! Clear ADC interrupt flag. */
25 ADC10IFG = 0x004 /*! Set ADC interrupt flag. */
26 };
27
28 /*! ADC10 Interrupt Enable */
29 enum ADC10IE_t {
30 ADC10IE_OFF = 0x000, /*! Disable ADC interrupt. */
31 ADC10IE = 0x008 /*! Enable ADC interrupt. */
32 };
33
34 /*! ADC10 On/Enable */
35 enum ADC10ON_t {
36 ADC10ON_OFF = 0x000, /*! Switch Off ADC10. */
37 ADC10ON = 0x010 /*! Switch On ADC10. */
38 };
39
40 /*! ADC10 Reference on */
41 enum REFON_t {
42 REFON_OFF = 0x000, /*! Disable ADC reference generator. */
43 REFON = 0x020 /*! Enable ADC reference generator. */
44 };
45
46 /*! ADC10 Ref 0:1.5V / 1:2.5V */
47 enum REF2_5V_t {
48 REF2_5V_OFF = 0x000, /*! Set reference voltage generator = 1.5V. */
49 REF2_5V = 0x040 /*! Set reference voltage generator = 2.5V. */
50 };
51
52 /*! ADC10 Multiple SampleConversion */
53 enum MSC_t {
54 MSC_OFF = 0x000, /*! Disable multiple sample and conversion. */
55 MSC = 0x080 /*! Enable multiple sample and conversion. */
56 };
57
58 /*! ADC10 Reference Burst Mode */
59 enum REFBURST_t {
60 REFBURST_OFF = 0x000, /*! Reference buffer on continuously. */
61 REFBURST = 0x100 /*! Reference buffer on only during sample-and-conversion. */
62 };
63
64 /*! ADC10 Enable output of Ref. */
65 enum REFOUT_t {
66 REFOUT_OFF = 0x000, /*! Reference output off. */
67 REFOUT = 0x200 /*! Reference output on. */
68 };
69
70 /*! ADC10 Sampling Rate 0:200ksps / 1:50ksps */
71 enum ADC10SR_t {
72 ADC10SR_OFF = 0x000, /*! Reference buffer supports up to ~200 ksps. */
73 ADC10SR = 0x400 /*! Reference buffer supports up to ~50 ksps. */
74 };
75
76 /*! ADC10 Sample Hold Select 0 */
77 enum ADC10SHT_t {
78 ADC10SHT_0 = (0*0x800u), /*! 4 x ADC10CLKs. */
79 ADC10SHT_1 = (1*0x800u), /*! 8 x ADC10CLKs. */
80 ADC10SHT_2 = (2*0x800u), /*! 16 x ADC10CLKs. */
81 ADC10SHT_3 = 3*0x800u /*! 64 x ADC10CLKs. */
82 };
83
84 /*! ADC10 Reference Select 0 */
85 enum SREF_t {
86 SREF_0 = (0*0x2000u), /*! VR+ = VCC and VR- = VSS. */
87 SREF_1 = (1*0x2000u), /*! VR+ = VREF+ and VR- = VSS. */
88 SREF_2 = (2*0x2000u), /*! VR+ = VeREF+ and VR- = VSS. */
89 SREF_3 = (3*0x2000u), /*! VR+ = Buffered VeREF+ and VR- = VSS. */
90 SREF_4 = (4*0x2000u), /*! VR+ = VCC and VR- = VREF-/ VeREF-. */
91 SREF_5 = (5*0x2000u), /*! VR+ = VREF+ and VR- = VREF-/ VeREF-. */
92 SREF_6 = (6*0x2000u), /*! VR+ = VeREF+ and VR- = VREF-/ VeREF-. */
93 SREF_7 = 7*0x2000u /*! VR+ = Buffered VeREF+ and VR- = VREF-/ VeREF-. */
94 };
95
96 enum ADC10BUSY_t {
97 ADC10BUSY_OFF = 0x0000, /*! No operation is active. */
98 ADC10BUSY = 0x0001 /*! A sequence, sample, or conversion is active. */
99 };
100
101 /*! Types of conversion */
102 enum CONSEQ_t {
103 CONSEQ_0 = (0*2u), /*! Single channel single conversion. */
104 CONSEQ_1 = (1*2u), /*! Sequence of channels. */
105 CONSEQ_2 = (2*2u), /*! Repeat single channel. */
106 CONSEQ_3 = 3*2u /*! Repeat sequence of channels. */
107 };
108
109 /*! ADC10 Clock Source */
110 enum ADC10SSEL_t {
111 ADC10SSEL_0 = (0*8u), /*! ADC10OSC. */
112 ADC10SSEL_1 = (1*8u), /*! ACLK. */
113 ADC10SSEL_2 = (2*8u), /*! MCLK.*/
114 ADC10SSEL_3 = 3*8u /*! SMCLK. */
115 };
116
117 /*! ADC10 Clock Divider */
118 enum ADC10DIV_t {
119 ADC10DIV_0 = (0*0x20u), /*! Divide by 1. */
120 ADC10DIV_1 = (1*0x20u), /*! Divide by 2. */
121 ADC10DIV_2 = (2*0x20u), /*! Divide by 3. */
122 ADC10DIV_3 = (3*0x20u), /*! Divide by 4. */
123 ADC10DIV_4 = (4*0x20u), /*! Divide by 5. */
124 ADC10DIV_5 = (5*0x20u), /*! Divide by 6. */
125 ADC10DIV_6 = (6*0x20u), /*! Divide by 7. */
126 ADC10DIV_7 = 7*0x20u /*! Divide by 8. */
127 };
128
129 /*! ADC10 input signal inversion */
130 enum ISSH_t {
131 ISSH_OFF = 0x0000, /*! Input signal not inverted. */
132 ISSH = 0x0100 /*! Input signal inverted. */
133 };
134
135 /*! ADC10 output as 2's complement */
136 enum ADC10DF_t {
137 ADC10DF_OFF = 0x0000, /*! ADC10 Data Format as binary. */
138 ADC10DF = 0x0200 /*! ADC10 Data Format as 2's complement */
139 };
140
141 /*! ADC10 trigger */
142 enum SHS_t {
143 SHS_0 = (0*0x400u), /*! ADC10SC. */
144 SHS_1 = (1*0x400u), /*! Timer A3 OUT1. */
145 SHS_2 = (2*0x400u), /*! Timer A3 OUT0. */
146 SHS_3 = 3*0x400u /*! Timer A3 OUT2. */
147 };
148
149 /*! ADC10 Channel Selection */
150 enum INCH_t {
151 INCH_0 = (0*0x1000u), /*! ADC Channel 0. */
152 INCH_1 = (1*0x1000u), /*! ADC Channel 1. */
153 INCH_2 = (2*0x1000u), /*! ADC Channel 2. */
154 INCH_3 = (3*0x1000u), /*! ADC Channel 3. */
155 INCH_4 = (4*0x1000u), /*! ADC Channel 4. */
156 INCH_5 = (5*0x1000u), /*! ADC Channel 5. */
157 INCH_6 = (6*0x1000u), /*! ADC Channel 6. */
158 INCH_7 = (7*0x1000u), /*! ADC Channel 7. */
159 INCH_8 = (8*0x1000u), /*! ADC VeRef+. */
160 INCH_9 = (9*0x1000u), /*! ADC VeRef-. */
161 INCH_10 = (10*0x1000u), /*! Temperature Sensor. */
162 INCH_11 = (11*0x1000u), /*! ADC convert VCC. */
163 INCH_12 = (12*0x1000u), /*! ADC Channel 12. */
164 INCH_13 = (13*0x1000u), /*! ADC Channel 13. */
165 INCH_14 = (14*0x1000u), /*! ADC Channel 14. */
166 INCH_15 = 15*0x1000u /*! ADC Channel 15. */
167 };
168
169 /*!
170 * ======== ADC10CT_t ========
171 * Data transfer modes
172 *
173 * @see #ADC10DTC0
174 */
175 enum ADC10CT_t {
176 ADC10CT_OFF = 0x000, /*! Data is transferred is stopped after every conversion. */
177 ADC10CT = 0x004 /*! Data is transferred continuously after every conversion. */
178 }
179
180 /*!
181 * ======== ADC10TB_t ========
182 * Block data transfer modes
183 *
184 * @see #ADC10DTC0
185 */
186 enum ADC10TB_t {
187 ADC10TB_OFF = 0x000, /*! One-block transfer mode. */
188 ADC10TB = 0x008 /*! Two-block transfer mode. */
189 }
190
191
192 /*!
193 * ======== ADC10CTL0_t ========
194 * ADC10 Control Register 0
195 *
196 * @see #ADC10CTL0
197 */
198 struct ADC10CTL0_t {
199 ADC10SC_t ADC10SC; /*! Start conversion. Software-controlled sample-and-conversion start.
200 * ADC10SC and ENC may be set together with one instruction. ADC10SC is
201 * reset automatically.
202 * 0 No sample-and-conversion start
203 * 1 Start sample-and-conversion */
204 ENC_t ENC; /*! Enable conversion
205 * 0 ADC10 disabled
206 * 1 ADC10 enabled */
207 ADC10IFG_t ADC10IFG; /*! ADC10 interrupt flag. This bit is set if ADC10MEM is loaded with a conversion
208 * result. It is automatically reset when the interrupt request is accepted, or it may
209 * be reset by software. When using the DTC this flag is set when a block of
210 * transfers is completed.
211 * 0 No interrupt pending
212 * 1 Interrupt pending */
213 ADC10IE_t ADC10IE; /*! ADC10 interrupt enable
214 * 0 Interrupt disabled
215 * 1 Interrupt enabled */
216 ADC10ON_t ADC10ON; /*! ADC10 on
217 * 0 ADC10 off
218 * 1 ADC10 on */
219 REFON_t REFON; /*! Reference generator on
220 * 0 Reference off
221 * 1 Reference on */
222 REF2_5V_t REF2_5V; /*! Reference-generator voltage. REFON must also be set.
223 * 0 1.5 V
224 * 1 2.5 V */
225 MSC_t MSC; /*! Multiple sample and conversion. Valid only for sequence or repeated modes.
226 * 0 The sampling requires a rising edge of the SHI signal to trigger each
227 * sample-and-conversion.
228 * 1 The first rising edge of the SHI signal triggers the sampling timer, but
229 * further sample-and-conversions are performed automatically as soon
230 * as the prior conversion is completed */
231 REFBURST_t REFBURST; /*! Reference burst.
232 * 0 Reference buffer on continuously
233 * 1 Reference buffer on only during sample-and-conversion */
234 REFOUT_t REFOUT; /*! Reference output
235 * 0 Reference output off
236 * 1 Reference output on */
237 ADC10SR_t ADC10SR; /*! ADC10 sampling rate. This bit selects the reference buffer drive capability for
238 * the maximum sampling rate. Setting ADC10SR reduces the current
239 * consumption of the reference buffer.
240 * 0 Reference buffer supports up to ~200 ksps
241 * 1 Reference buffer supports up to ~50 ksps */
242 ADC10SHT_t ADC10SHT; /*! ADC10 sample-and-hold time
243 * 00 4 x ADC10CLKs
244 * 01 8 x ADC10CLKs
245 * 10 16 x ADC10CLKs
246 * 11 64 x ADC10CLKs */
247 SREF_t SREF; /*! Select reference
248 * 000 VR+ = VCC and VR- = VSS
249 * 001 VR+ = VREF+ and VR- = VSS
250 * 010 VR+ = VeREF+ and VR- = VSS
251 * 011 VR+ = Buffered VeREF+ and VR- = VSS
252 * 100 VR+ = VCC and VR- = VREF-/ VeREF-
253 * 101 VR+ = VREF+ and VR- = VREF-/ VeREF-
254 * 110 VR+ = VeREF+ and VR- = VREF-/ VeREF-
255 * 111 VR+ = Buffered VeREF+ and VR- = VREF-/ VeREF- */
256 }
257
258 /*!
259 * ======== ADC10CTL1_t ========
260 * ADC10 Control Register 1
261 *
262 * @see #ADC10CTL1
263 */
264 struct ADC10CTL1_t {
265 ADC10BUSY_t ADC10BUSY; /*! ADC10 busy. This bit indicates an active sample or conversion operation
266 * 0 No operation is active.
267 * 1 A sequence, sample, or conversion is active. */
268 CONSEQ_t CONSEQ; /*! Conversion sequence mode select
269 * 00 Single-channel-single-conversion
270 * 01 Sequence-of-channels
271 * 10 Repeat-single-channel
272 * 11 Repeat-sequence-of-channels */
273 ADC10SSEL_t ADC10SSEL; /*! ADC10 clock source select
274 * 00 ADC10OSC
275 * 01 ACLK
276 * 10 MCLK
277 * 11 SMCLK */
278 ADC10DIV_t ADC10DIV; /*! ADC10 clock divider
279 * 000 /1
280 * 001 /2
281 * 010 /3
282 * 011 /4
283 * 100 /5
284 * 101 /6
285 * 110 /7
286 * 111 /8 */
287 ISSH_t ISSH; /*! Invert signal sample-and-hold
288 * 0 The sample-input signal is not inverted.
289 * 1 The sample-input signal is inverted. */
290 ADC10DF_t ADC10DF; /*! ADC10 data format
291 * 0 Straight binary
292 * 1 2s complement */
293 SHS_t SHS; /*! Sample-and-hold source select
294 * 00 ADC10SC bit
295 * 01 Timer_A.OUT1
296 * 10 Timer_A.OUT0
297 * 11 Timer_A.OUT2 (Timer_A.OUT1 on MSP430x20x2 devices) */
298 INCH_t INCH; /*! Input channel select. These bits select the channel for a single-conversion or
299 * the highest channel for a sequence of conversions.
300 * 0000 A0
301 * 0001 A1
302 * 0010 A2
303 * 0011 A3
304 * 0100 A4
305 * 0101 A5
306 * 0110 A6
307 * 0111 A7
308 * 1000 VeREF+
309 * 1001 VREF-/VeREF-
310 * 1010 Temperature sensor
311 * 1011 (VCC ? VSS) / 2
312 * 1100 A12
313 * 1101 A13
314 * 1110 A14
315 * 1111 A15 */
316 }
317
318 /*!
319 * ======== ADC10DTC0_t ========
320 * Data Transfer Control Register 0
321 *
322 * @see #ADC10DTC0
323 */
324 struct ADC10DTC0_t {
325 ADC10TB_t ADC10TB; /*! ADC10 two-block mode
326 * 0 One-block transfer mode
327 * 1 Two-block transfer mode */
328 ADC10CT_t ADC10CT; /*! ADC10 continuous transfer
329 * 0 Data transfer stops when one block (one-block mode) or two blocks
330 * (two-block mode) have completed.
331 * 1 Data is transferred continuously. DTC operation is stopped only if
332 * ADC10CT cleared, or ADC10SA is written to. */
333 }
334
335 /*!
336 * ======== create ========
337 * Create an instance of this peripheral
338 */
339 create(IClock.Instance clock, ITimer_A.Instance timerA);
340
341 instance:
342 /*! Control Register 0 */
343 config ADC10CTL0_t ADC10CTL0 = {
344 ADC10SC : ADC10SC_OFF,
345 ENC : ENC_OFF,
346 ADC10IFG: ADC10IFG_OFF,
347 ADC10IE : ADC10IE_OFF,
348 ADC10ON : ADC10ON_OFF,
349 REFON : REFON_OFF,
350 REF2_5V : REF2_5V_OFF,
351 MSC : MSC_OFF,
352 REFBURST: REFBURST_OFF,
353 REFOUT : REFOUT_OFF,
354 ADC10SR : ADC10SR_OFF,
355 ADC10SHT: ADC10SHT_0,
356 SREF : SREF_0
357 };
358
359 /*! Control Register 1 */
360 config ADC10CTL1_t ADC10CTL1 = {
361 ADC10BUSY : ADC10BUSY_OFF,
362 CONSEQ : CONSEQ_0,
363 ADC10SSEL : ADC10SSEL_0,
364 ADC10DIV : ADC10DIV_0,
365 ISSH : ISSH_OFF,
366 ADC10DF : ADC10DF_OFF,
367 SHS : SHS_0,
368 INCH : INCH_0
369 };
370
371 /*!
372 * Analog (Input) Enable Control Register 0
373 *
374 * Bit n enables the corresponding pin for analog
375 * input. Bit 0 corresponds to A0, bit 1 corresponds to A1, ...
376 */
377 config Bits16 ADC10AE0 = 0;
378
379 /*!
380 * Analog (Input) Enable Control Register 1
381 *
382 * Bits 0, 1, 2, and 3 are reserved.
383 *
384 * Starting with bit 4, bit n enables pin n+8 for analog
385 * input: Bit 4 corresponds to A12, bit 5 corresponds to A13, ...
386 */
387 config Bits16 ADC10AE1 = 0;
388
389 /*! Data Transfer Control Register 0 */
390 config ADC10DTC0_t ADC10DTC0 = {
391 ADC10TB : ADC10TB_OFF,
392 ADC10CT : ADC10CT_OFF
393 };
394
395 /*!
396 * Data Transfer Control Register 1
397 *
398 * This register defines the number of transfers in each block: 0
399 * implies DTC is disabled, 1 through 0xff are valid transfer counts.
400 */
401 config Bits8 ADC10DTC1 = 0;
402
403 /*! Data Transfer Start Address */
404 config Bits16 ADC10SA = 0x200;
405
406 /*! @_nodoc */
407 config IClock.Instance clock;
408
409 /*! @_nodoc */
410 config ITimer_A.Instance timerA;
411 }