1 2 3 4 5 6 7 8 9 10 11
12
13 /*!
14 * ======== IMSP430x22xx.xdc ========
15 * Common definition for MSP430x22xx devices
16 */
17
18 metaonly interface IMSP430x22xx inherits IMSP430
19 {
20
21 instance:
22
23 config ti.catalog.msp430.peripherals.timer.Timer_A3.Instance timer_A3;
24 config ti.catalog.msp430.peripherals.timer.Timer_B3.Instance timer_B3;
25
26 config ti.catalog.msp430.peripherals.clock.Clock2xx.Instance clock;
27 config ti.catalog.msp430.peripherals.communication.USCI_A0_UART_2xx.Instance usci_A0_UART;
28 config ti.catalog.msp430.peripherals.communication.USCI_A0_SPI_2xx.Instance usci_A0_SPI;
29 config ti.catalog.msp430.peripherals.communication.USCI_B0_SPI_2xx.Instance usci_B0_SPI;
30 config ti.catalog.msp430.peripherals.communication.USCI_B0_I2C_2xx.Instance usci_B0_I2C;
31 config ti.catalog.msp430.peripherals.adc.ADC10.Instance adc10;
32 config ti.catalog.msp430.peripherals.watchdog.WDTPlus.Instance wdtPlus;
33 config ti.catalog.msp430.peripherals.oa.OA_2.Instance oa;
34 config ti.catalog.msp430.peripherals.gpio.GPIO_MSP430x22xx.Instance gpio;
35 config ti.catalog.msp430.peripherals.memory.Flash_2xx.Instance flash;
36 config ti.catalog.msp430.peripherals.special_function.IE1.Instance interruptEnableRegister1;
37 config ti.catalog.msp430.peripherals.special_function.IE2.Instance interruptEnableRegister2;
38
39 /*!
40 * ======== commonMap ========
41 * Memory map elements shared by all MSP430x22xx devices
42 */
43 config xdc.platform.IPlatform.Memory commonMap[string] = [
44 ["PERIPHERALS_8BIT", {
45 comment: "Memory mapped I/O registers",
46 name: "PERIPHERALS_8BIT",
47 base: 0x0010,
48 len: 0x00F0,
49 space: "io",
50 access: "RW"
51 }],
52
53 ["PERIPHERALS_16BIT", {
54 comment: "Memory mapped I/O registers",
55 name: "PERIPHERALS_16BIT",
56 base: 0x0100,
57 len: 0x0100,
58 space: "io",
59 access: "RW"
60 }],
61
62 ["BSLSKEY", {
63 comment: "Boot loader security key",
64 name: "BSLSKEY",
65 base: 0xFFDE,
66 len: 0x0002,
67 space: "data",
68 access: "RI"
69 }],
70
71 ["INT00", {
72 comment: "Reserved Vector (int00)",
73 name: "INT00",
74 base: 0xFFE0,
75 len: 0x0002,
76 space: "data",
77 access: "RW"
78 }],
79
80 ["INT01", {
81 comment: "Reserved Vector (int01)",
82 name: "INT01",
83 base: 0xFFE2,
84 len: 0x0002,
85 space: "data",
86 access: "RW"
87 }],
88
89 ["INT02", {
90 comment: "I/O Port P1 Vector (int02)",
91 name: "INT02",
92 base: 0xFFE4,
93 len: 0x0002,
94 space: "data",
95 access: "RW"
96 }],
97
98 ["INT03", {
99 comment: "I/O Port P2 Vector (int03)",
100 name: "INT03",
101 base: 0xFFE6,
102 len: 0x0002,
103 space: "data",
104 access: "RW"
105 }],
106
107 ["INT04", {
108 comment: "Reserved Vector (int04)",
109 name: "INT04",
110 base: 0xFFE8,
111 len: 0x0002,
112 space: "data",
113 access: "RW"
114 }],
115
116 ["INT05", {
117 comment: "ADC10 Vector (int05)",
118 name: "INT05",
119 base: 0xFFEA,
120 len: 0x0002,
121 space: "data",
122 access: "RW"
123 }],
124
125 ["INT06", {
126 comment: "USCI_A0/B0 Transmit Vector (int06)",
127 name: "INT06",
128 base: 0xFFEC,
129 len: 0x0002,
130 space: "data",
131 access: "RW"
132 }],
133
134 ["INT07", {
135 comment: "USCI_A0/B0 Receive Vector (int07)",
136 name: "INT07",
137 base: 0xFFEE,
138 len: 0x0002,
139 space: "data",
140 access: "RW"
141 }],
142
143 ["INT08", {
144 comment: "Timer_A3 TBCCR1 Vector (int08)",
145 name: "INT08",
146 base: 0xFFF0,
147 len: 0x0002,
148 space: "data",
149 access: "RW"
150 }],
151
152 ["INT09", {
153 comment: "Timer_A3 TBCCR0 Vector (int09)",
154 name: "INT09",
155 base: 0xFFF2,
156 len: 0x0002,
157 space: "data",
158 access: "RW"
159 }],
160
161 ["INT10", {
162 comment: "Watchdog Vector (int10)",
163 name: "INT10",
164 base: 0xFFF4,
165 len: 0x0002,
166 space: "data",
167 access: "RW"
168 }],
169
170 ["INT11", {
171 comment: "Reserved Vector (int11)",
172 name: "INT11",
173 base: 0xFFF6,
174 len: 0x0002,
175 space: "data",
176 access: "RW"
177 }],
178
179 ["INT12", {
180 comment: "Timer_B3 TBCCR1 Vector (int12)",
181 name: "INT12",
182 base: 0xFFF8,
183 len: 0x0002,
184 space: "data",
185 access: "RW"
186 }],
187
188 ["INT13", {
189 comment: "Timer_B3 TBCCR0 Vector (int13)",
190 name: "INT13",
191 base: 0xFFFA,
192 len: 0x0002,
193 space: "data",
194 access: "RW"
195 }],
196
197 ["INT14", {
198 comment: "NMI Vector (int14)",
199 name: "INT14",
200 base: 0xFFFC,
201 len: 0x0002,
202 space: "data",
203 access: "RW"
204 }],
205
206 ["RESET", {
207 comment: "Reset Vector (int15)",
208 name: "RESET",
209 base: 0xFFFE,
210 len: 0x0002,
211 space: "data",
212 access: "RW"
213 }],
214
215 ["INFOA", {
216 comment: "INFO Flash Memory Segment A",
217 name: "INFOA",
218 base: 0x10C0,
219 len: 0x0040,
220 space: "data",
221 access: "RW"
222 }],
223
224 ["INFOB", {
225 comment: "INFO Flash Memory Segment B",
226 name: "INFOB",
227 base: 0x1080,
228 len: 0x0040,
229 space: "data",
230 access: "RW"
231 }],
232
233 ["INFOC", {
234 comment: "INFO Flash Memory Segment C",
235 name: "INFOC",
236 base: 0x1040,
237 len: 0x0040,
238 space: "data",
239 access: "RW"
240 }],
241
242 ["INFOD", {
243 comment: "INFO Flash Memory Segment D",
244 name: "INFOD",
245 base: 0x1000,
246 len: 0x0040,
247 space: "data",
248 access: "RW"
249 }],
250 ];
251 }