1 /*
2 * Copyright (c) 2010 by Texas Instruments and others.
3 * All rights reserved. This program and the accompanying materials
4 * are made available under the terms of the Eclipse Public License v1.0
5 * which accompanies this distribution, and is available at
6 * http://www.eclipse.org/legal/epl-v10.html
7 *
8 * Contributors:
9 * Texas Instruments - initial implementation
10 *
11 * */
12
13 /*
14 * ======== TMS320CF761990.xdc ========
15 *
16 */
17 package ti.catalog.c6000;
18
19 /*!
20 * ======== TMS320CF761990 ========
21 * The C64P device data sheet module.
22 *
23 * This module implements the xdc.platform.ICpuDataSheet interface and is
24 * used by platforms to obtain "data sheet" information about this device.
25 */
26 metaonly module TMS320CF761990 inherits ti.catalog.ICpuDataSheet
27 {
28
29 config long cacheSizeL1[string] = [
30 ["0k", 0x0000],
31 ["4k", 0x1000],
32 ["8k", 0x2000],
33 ["16k", 0x4000],
34 ["32k", 0x8000],
35 ];
36
37 config long cacheSizeL2[string] = [
38 ["0k", 0x00000],
39 ["32k", 0x08000],
40 ["64k", 0x10000]
41 ];
42
43 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
44 ['l1PMode',{desc:"L1P Cache",
45 map : [["0k",0x0000],
46 ["4k",0x1000],
47 ["8k",0x2000],
48 ["16k",0x4000],
49 ["32k",0x8000]],
50 defaultValue: "0k",
51 memorySection: "L1PSRAM"}],
52
53 ['l1DMode',{desc:"L1D Cache",
54 map : [["0k",0x0000],
55 ["4k",0x1000],
56 ["8k",0x2000],
57 ["16k",0x4000],
58 ["32k",0x8000]],
59 defaultValue: "0k",
60 memorySection: "L1DSRAM"}],
61
62 ['l2Mode',{desc:"L2 Cache",
63 map : [["0k",0x0000],
64 ["32k",0x8000],
65 ["64k",0x10000]],
66 defaultValue: "0k",
67 memorySection: "IRAM"}],
68
69 ];
70
71 instance:
72 override config int minProgUnitSize = 1;
73 override config int minDataUnitSize = 1;
74 override config int dataWordSize = 4;
75
76 override config string cpuCore = "F761990";
77 override config string isa = "64P";
78 override config string cpuCoreRevision = "1.0";
79
80 config xdc.platform.IPlatform.Memory memMap[string] = [
81 ["IRAM", {
82 comment: "Internal 64KB L2 UMAP0 memory",
83 name: "IRAM",
84 base: 0x11800000,
85 len: 0x00010000,
86 space: "code/data",
87 access: "RWX"
88 }],
89
90 ["L1PSRAM", {
91 comment: "Internal 32KB L1 program memory",
92 name: "L1PSRAM",
93 base: 0x11E08000,
94 len: 0x00008000,
95 space: "code",
96 access: "RWX"
97 }],
98
99 ["L1DSRAM", {
100 comment: "Internal 80KB L1 data memory",
101 name: "L1DSRAM",
102 base: 0x11F04000,
103 len: 0x00014000,
104 space: "data",
105 access: "RW"
106 }],
107
108 ["ARM_RAM0", {
109 comment: "Internal ARM RAM instruction memory",
110 name: "ARM_RAM0",
111 base: 0x02000000,
112 len: 0x00008000,
113 space: "code",
114 access: "RWX"
115 }],
116
117 ["ARM_RAM1", {
118 comment: "Internal ARM RAM data memory",
119 name: "ARM_RAM1",
120 base: 0x02008000,
121 len: 0x00004000,
122 space: "data",
123 access: "RW"
124 }],
125 ];
126 };
127 /*
128 * @(#) ti.catalog.c6000; 1, 0, 0, 0,263; 5-25-2010 17:25:13; /db/ztree/library/trees/platform/platform-l15x/src/
129 */
130