1 /*
2 * Copyright (c) 2010 by Texas Instruments and others.
3 * All rights reserved. This program and the accompanying materials
4 * are made available under the terms of the Eclipse Public License v1.0
5 * which accompanies this distribution, and is available at
6 * http://www.eclipse.org/legal/epl-v10.html
7 *
8 * Contributors:
9 * Texas Instruments - initial implementation
10 *
11 * */
12
13 /*
14 * ======== ITMS320C6452.xdc ========
15 *
16 */
17 package ti.catalog.c6000;
18
19 /*!
20 * ======== ITMS320C6452 ========
21 * The interface for 6452 and similar devices' data sheet module.
22 *
23 * This module implements the ICpuDataSheet interface and is
24 * used by platforms to obtain "data sheet" information about this device.
25 */
26 metaonly interface ITMS320C6452 inherits ti.catalog.ICpuDataSheet
27 {
28
29 config long cacheSizeL1[string] = [
30 ["0k", 0x0000],
31 ["4k", 0x1000],
32 ["8k", 0x2000],
33 ["16k", 0x4000],
34 ["32k", 0x8000],
35 ];
36
37 config long cacheSizeL2[string] = [
38 ["0k", 0x00000],
39 ["32k", 0x08000],
40 ["64k", 0x10000],
41 ["128k", 0x20000],
42 ["256k", 0x40000]
43 ];
44
45 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
46 ['l1PMode',{desc:"L1P Cache",
47 map : [["0k",0x0000],
48 ["4k",0x1000],
49 ["8k",0x2000],
50 ["16k",0x4000],
51 ["32k",0x8000]],
52 defaultValue: "0k",
53 memorySection: "L1PSRAM"}],
54
55 ['l1DMode',{desc:"L1D Cache",
56 map : [["0k",0x0000],
57 ["4k",0x1000],
58 ["8k",0x2000],
59 ["16k",0x4000],
60 ["32k",0x8000]],
61 defaultValue: "0k",
62 memorySection: "L1DSRAM"}],
63
64 ['l2Mode',{desc:"L2 Cache",
65 map : [["0k",0x0000],
66 ["32k",0x8000],
67 ["64k",0x10000],
68 ["128k",0x20000],
69 ["256k",0x40000]],
70 defaultValue: "0k",
71 memorySection: "IRAM"}],
72 ];
73
74 instance:
75
76 override config string cpuCore = "64x+";
77 override config string isa = "64P";
78 override config string cpuCoreRevision = "1.0";
79
80 override config int minProgUnitSize = 1;
81 override config int minDataUnitSize = 1;
82 override config int dataWordSize = 4;
83
84 /*!
85 * ======== memMap ========
86 * The default memory map for this device
87 */
88 config xdc.platform.IPlatform.Memory memMap[string] = [
89 ["IRAM", {
90 comment: "Internal 1408KB L2 RAM/CACHE",
91 name: "IRAM",
92 base: 0xA00000,
93 len: 0x160000,
94 space: "code/data",
95 access: "RWX"
96 }],
97
98 ["L1PSRAM", {
99 comment: "Internal 32KB RAM/CACHE L1 program memory",
100 name: "L1PSRAM",
101 base: 0xE00000,
102 len: 0x008000,
103 space: "code",
104 access: "RWX"
105 }],
106
107 ["L1DSRAM", {
108 comment: "Internal 32KB RAM/CACHE L1 data memory",
109 name: "L1DSRAM",
110 base: 0xF00000,
111 len: 0x008000,
112 space: "data",
113 access: "RW"
114 }],
115
116 ];
117 };
118 /*
119 * @(#) ti.catalog.c6000; 1, 0, 0, 0,263; 5-25-2010 17:25:11; /db/ztree/library/trees/platform/platform-l15x/src/
120 */
121