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12
13 /*!
14 * ======== IMSP430x22xx.xdc ========
15 * Common definition for MSP430x22xx devices
16 */
17
18 metaonly interface IMSP430x22xx inherits IMSP430
19 {
20 struct Timer {
21 string name;
22 UInt baseAddr;
23 UInt intNum;
24 };
25
26 instance:
27
28 /*!
29 * ======== commonMap ========
30 * Memory map elements shared by all MSP430x22xx devices
31 */
32 config xdc.platform.IPlatform.Memory commonMap[string] = [
33 ["PERIPHERALS_8BIT", {
34 comment: "Memory mapped I/O registers",
35 name: "PERIPHERALS_8BIT",
36 base: 0x0010,
37 len: 0x00F0,
38 space: "io",
39 access: "RW"
40 }],
41
42 ["PERIPHERALS_16BIT", {
43 comment: "Memory mapped I/O registers",
44 name: "PERIPHERALS_16BIT",
45 base: 0x0100,
46 len: 0x0100,
47 space: "io",
48 access: "RW"
49 }],
50
51 ["BSLSKEY", {
52 comment: "Boot loader security key",
53 name: "BSLSKEY",
54 base: 0xFFDE,
55 len: 0x0002,
56 space: "data",
57 access: "RI"
58 }],
59
60 ["INT00", {
61 comment: "Reserved Vector (int00)",
62 name: "INT00",
63 base: 0xFFE0,
64 len: 0x0002,
65 space: "data",
66 access: "RW"
67 }],
68
69 ["INT01", {
70 comment: "Reserved Vector (int01)",
71 name: "INT01",
72 base: 0xFFE2,
73 len: 0x0002,
74 space: "data",
75 access: "RW"
76 }],
77
78 ["IOPORT1", {
79 comment: "I/O Port P1 Vector (int02)",
80 name: "IOPORT1",
81 base: 0xFFE4,
82 len: 0x0002,
83 space: "data",
84 access: "RW"
85 }],
86
87 ["IOPORT2", {
88 comment: "I/O Port P2 Vector (int03)",
89 name: "IOPORT2",
90 base: 0xFFE6,
91 len: 0x0002,
92 space: "data",
93 access: "RW"
94 }],
95
96 ["INT04", {
97 comment: "Reserved Vector (int04)",
98 name: "INT04",
99 base: 0xFFE8,
100 len: 0x0002,
101 space: "data",
102 access: "RW"
103 }],
104
105 ["ADC10", {
106 comment: "ADC10 Vector (int05)",
107 name: "ADC10",
108 base: 0xFFEA,
109 len: 0x0002,
110 space: "data",
111 access: "RW"
112 }],
113
114 ["USCI_TX", {
115 comment: "USCI_A0/B0 Transmit Vector (int06)",
116 name: "USCI_TX",
117 base: 0xFFEC,
118 len: 0x0002,
119 space: "data",
120 access: "RW"
121 }],
122
123 ["USCI_RX", {
124 comment: "USCI_A0/B0 Receive Vector (int07)",
125 name: "USCI_RX",
126 base: 0xFFEE,
127 len: 0x0002,
128 space: "data",
129 access: "RW"
130 }],
131
132 ["TIMER_A1", {
133 comment: "Timer_A3 TBCCR1 Vector (int08)",
134 name: "TIMER_A1",
135 base: 0xFFF0,
136 len: 0x0002,
137 space: "data",
138 access: "RW"
139 }],
140
141 ["TIMER_A0", {
142 comment: "Timer_A3 TBCCR0 Vector (int09)",
143 name: "TIMER_A0",
144 base: 0xFFF2,
145 len: 0x0002,
146 space: "data",
147 access: "RW"
148 }],
149
150 ["INT10", {
151 comment: "Watchdog Vector (int10)",
152 name: "INT10",
153 base: 0xFFF4,
154 len: 0x0002,
155 space: "data",
156 access: "RW"
157 }],
158
159 ["INT11", {
160 comment: "Reserved Vector (int11)",
161 name: "INT11",
162 base: 0xFFF6,
163 len: 0x0002,
164 space: "data",
165 access: "RW"
166 }],
167
168 ["TIMER_B1", {
169 comment: "Timer_B3 TBCCR1 Vector (int12)",
170 name: "TIMER_B1",
171 base: 0xFFF8,
172 len: 0x0002,
173 space: "data",
174 access: "RW"
175 }],
176
177 ["TIMER_B0", {
178 comment: "Timer_B3 TBCCR0 Vector (int13)",
179 name: "TIMER_B0",
180 base: 0xFFFA,
181 len: 0x0002,
182 space: "data",
183 access: "RW"
184 }],
185
186 ["NMI", {
187 comment: "NMI Vector (int14)",
188 name: "NMI",
189 base: 0xFFFC,
190 len: 0x0002,
191 space: "data",
192 access: "RW"
193 }],
194
195 ["RESET", {
196 comment: "Reset Vector (int15)",
197 name: "RESET",
198 base: 0xFFFE,
199 len: 0x0002,
200 space: "data",
201 access: "RW"
202 }],
203
204 ["INFO", {
205 comment: "Information FLASH",
206 name: "INFO",
207 base: 0x1000,
208 len: 0x0100,
209 space: "data",
210 access: "RW"
211 }],
212 ];
213
214 config Timer timers[2] = [
215 {
216 name: "Timer_A3",
217 baseAddr: 0x160,
218 intNum: 25
219 },
220
221 {
222 name: "Timer_B3",
223 baseAddr: 0x180,
224 intNum: 29
225 },
226 ];
227 }
228 229 230
231