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13 /*!
14 * ======== IMSP430x22xx.xdc ========
15 * Common definition for MSP430x22xx devices
16 */
17
18 metaonly interface IMSP430x22xx inherits IMSP430
19 {
20 instance:
21
22 /*!
23 * ======== commonMap ========
24 * Memory map elements shared by all MSP430x22xx devices
25 */
26 config xdc.platform.IPlatform.Memory commonMap[string] = [
27 ["PERIPHERALS_8BIT", {
28 comment: "Memory mapped I/O registers",
29 name: "PERIPHERALS_8BIT",
30 base: 0x0010,
31 len: 0x00F0,
32 space: "io",
33 access: "RW"
34 }],
35
36 ["PERIPHERALS_16BIT", {
37 comment: "Memory mapped I/O registers",
38 name: "PERIPHERALS_16BIT",
39 base: 0x0100,
40 len: 0x0100,
41 space: "io",
42 access: "RW"
43 }],
44
45 ["BSLSKEY", {
46 comment: "Boot loader security key",
47 name: "BSLSKEY",
48 base: 0xFFDE,
49 len: 0x0002,
50 space: "data",
51 access: "RI"
52 }],
53
54 ["INT00", {
55 comment: "Reserved Vector (int00)",
56 name: "INT00",
57 base: 0xFFE0,
58 len: 0x0002,
59 space: "data",
60 access: "RW"
61 }],
62
63 ["INT01", {
64 comment: "Reserved Vector (int01)",
65 name: "INT01",
66 base: 0xFFE2,
67 len: 0x0002,
68 space: "data",
69 access: "RW"
70 }],
71
72 ["IOPORT1", {
73 comment: "I/O Port P1 Vector (int02)",
74 name: "IOPORT1",
75 base: 0xFFE4,
76 len: 0x0002,
77 space: "data",
78 access: "RW"
79 }],
80
81 ["IOPORT2", {
82 comment: "I/O Port P2 Vector (int03)",
83 name: "IOPORT2",
84 base: 0xFFE6,
85 len: 0x0002,
86 space: "data",
87 access: "RW"
88 }],
89
90 ["INT04", {
91 comment: "Reserved Vector (int04)",
92 name: "INT04",
93 base: 0xFFE8,
94 len: 0x0002,
95 space: "data",
96 access: "RW"
97 }],
98
99 ["ADC10", {
100 comment: "ADC10 Vector (int05)",
101 name: "ADC10",
102 base: 0xFFEA,
103 len: 0x0002,
104 space: "data",
105 access: "RW"
106 }],
107
108 ["USCI_TX", {
109 comment: "USCI_A0/B0 Transmit Vector (int06)",
110 name: "USCI_TX",
111 base: 0xFFEC,
112 len: 0x0002,
113 space: "data",
114 access: "RW"
115 }],
116
117 ["USCI_RX", {
118 comment: "USCI_A0/B0 Receive Vector (int07)",
119 name: "USCI_RX",
120 base: 0xFFEE,
121 len: 0x0002,
122 space: "data",
123 access: "RW"
124 }],
125
126 ["TIMER_A1", {
127 comment: "Timer_A3 TBCCR1 Vector (int08)",
128 name: "TIMER_A1",
129 base: 0xFFF0,
130 len: 0x0002,
131 space: "data",
132 access: "RW"
133 }],
134
135 ["TIMER_A0", {
136 comment: "Timer_A3 TBCCR0 Vector (int09)",
137 name: "TIMER_A0",
138 base: 0xFFF2,
139 len: 0x0002,
140 space: "data",
141 access: "RW"
142 }],
143
144 ["INT10", {
145 comment: "Watchdog Vector (int10)",
146 name: "INT10",
147 base: 0xFFF4,
148 len: 0x0002,
149 space: "data",
150 access: "RW"
151 }],
152
153 ["INT11", {
154 comment: "Reserved Vector (int11)",
155 name: "INT11",
156 base: 0xFFF6,
157 len: 0x0002,
158 space: "data",
159 access: "RW"
160 }],
161
162 ["TIMER_B1", {
163 comment: "Timer_B3 TBCCR1 Vector (int12)",
164 name: "TIMER_B1",
165 base: 0xFFF8,
166 len: 0x0002,
167 space: "data",
168 access: "RW"
169 }],
170
171 ["TIMER_B0", {
172 comment: "Timer_B3 TBCCR0 Vector (int13)",
173 name: "TIMER_B0",
174 base: 0xFFFA,
175 len: 0x0002,
176 space: "data",
177 access: "RW"
178 }],
179
180 ["NMI", {
181 comment: "NMI Vector (int14)",
182 name: "NMI",
183 base: 0xFFFC,
184 len: 0x0002,
185 space: "data",
186 access: "RW"
187 }],
188
189 ["RESET", {
190 comment: "Reset Vector (int15)",
191 name: "RESET",
192 base: 0xFFFE,
193 len: 0x0002,
194 space: "data",
195 access: "RW"
196 }],
197
198 ["INFO", {
199 comment: "Information FLASH",
200 name: "INFO",
201 base: 0x1000,
202 len: 0x0100,
203 space: "data",
204 access: "RW"
205 }],
206 ];
207 }
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